diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index 29130e766..d6fb995b1 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -181,13 +181,13 @@ localparam ZCF_SUPPORTED = 0; localparam ZCD_SUPPORTED = 0; // K extension instructions -localparam ZBKB_SUPPORTED = 0; -localparam ZBKC_SUPPORTED = 0; -localparam ZBKX_SUPPORTED = 0; -localparam ZKNE_SUPPORTED = 0; -localparam ZKND_SUPPORTED = 0; -localparam ZK_SUPPORTED = 0; -localparam ZKNH_SUPPORTED = 0; +localparam ZBKB_SUPPORTED = 1; +localparam ZBKC_SUPPORTED = 1; +localparam ZBKX_SUPPORTED = 1; +localparam ZKND_SUPPORTED = 1; +localparam ZKNE_SUPPORTED = 1; +localparam ZKNH_SUPPORTED = 1; +localparam ZK_SUPPORTED = 1; // Memory synthesis configuration localparam USE_SRAM = 0; diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh index a483ccbc4..1d6c5e9f4 100644 --- a/config/rv64gc/config.vh +++ b/config/rv64gc/config.vh @@ -182,13 +182,13 @@ localparam ZCF_SUPPORTED = 0; localparam ZCD_SUPPORTED = 0; // K extension instructions -localparam ZBKB_SUPPORTED = 0; -localparam ZBKC_SUPPORTED = 0; -localparam ZBKX_SUPPORTED = 0; -localparam ZKNE_SUPPORTED = 0; -localparam ZKND_SUPPORTED = 0; -localparam ZK_SUPPORTED = 0; -localparam ZKNH_SUPPORTED = 0; +localparam ZBKB_SUPPORTED = 1; +localparam ZBKC_SUPPORTED = 1; +localparam ZBKX_SUPPORTED = 1; +localparam ZKND_SUPPORTED = 1; +localparam ZKNE_SUPPORTED = 1; +localparam ZKNH_SUPPORTED = 1; +localparam ZK_SUPPORTED = 1; // Memory synthesis configuration localparam USE_SRAM = 0; diff --git a/config/shared/config-shared.vh b/config/shared/config-shared.vh index be5543967..954c45d7d 100644 --- a/config/shared/config-shared.vh +++ b/config/shared/config-shared.vh @@ -29,6 +29,7 @@ localparam D_SUPPORTED = ((MISA >> 3) % 2 == 1); localparam E_SUPPORTED = ((MISA >> 4) % 2 == 1); localparam F_SUPPORTED = ((MISA >> 5) % 2 == 1); localparam I_SUPPORTED = ((MISA >> 8) % 2 == 1); +localparam K_SUPPORTED = ((ZBKB_SUPPORTED | ZBKC_SUPPORTED | ZBKX_SUPPORTED | ZKND_SUPPORTED | ZKNE_SUPPORTED | ZKNH_SUPPORTED)); localparam M_SUPPORTED = ((MISA >> 12) % 2 == 1); localparam Q_SUPPORTED = ((MISA >> 16) % 2 == 1); localparam S_SUPPORTED = ((MISA >> 18) % 2 == 1); diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh index 464e3c0f9..5635b286c 100644 --- a/config/shared/parameter-defs.vh +++ b/config/shared/parameter-defs.vh @@ -113,6 +113,13 @@ localparam cvw_t P = '{ ZCB_SUPPORTED : ZCB_SUPPORTED, ZCD_SUPPORTED : ZCD_SUPPORTED, ZCF_SUPPORTED : ZCF_SUPPORTED, + ZBKB_SUPPORTED: ZBKB_SUPPORTED, + ZBKC_SUPPORTED: ZBKC_SUPPORTED, + ZBKX_SUPPORTED: ZBKX_SUPPORTED, + ZKND_SUPPORTED: ZKND_SUPPORTED, + ZKNE_SUPPORTED: ZKNE_SUPPORTED, + ZKNH_SUPPORTED: ZKNH_SUPPORTED, + ZK_SUPPORTED : ZK_SUPPORTED, USE_SRAM : USE_SRAM, M_MODE : M_MODE, S_MODE : S_MODE, @@ -136,6 +143,7 @@ localparam cvw_t P = '{ E_SUPPORTED : E_SUPPORTED, F_SUPPORTED : F_SUPPORTED, I_SUPPORTED : I_SUPPORTED, + K_SUPPORTED : K_SUPPORTED, M_SUPPORTED : M_SUPPORTED, Q_SUPPORTED : Q_SUPPORTED, S_SUPPORTED : S_SUPPORTED, diff --git a/sim/regression-wally b/sim/regression-wally index d06ac0b28..1d12a04ec 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -88,7 +88,7 @@ for test in tests64i: configs.append(tc) tests32gcimperas = ["imperas32i", "imperas32f", "imperas32m", "imperas32c"] # unused -tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32f_divsqrt", "arch32d_divsqrt", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbs", "arch32zfh", "arch32zfh_fma", "arch32zfh_divsqrt", "arch32zfaf", "wally32a", "wally32priv", "wally32periph"] # "arch32zbc", "arch32zfad", +tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32f_divsqrt", "arch32d_divsqrt", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbs", "arch32zfh", "arch32zfh_fma", "arch32zfh_divsqrt", "arch32zfaf", "wally32a", "wally32priv", "wally32periph", "arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh"] # "arch32zbc", "arch32zfad", #tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zicboz", "arch32zcb", "wally32a", "wally32priv", "wally32periph"] for test in tests32gc: tc = TestCase( @@ -127,7 +127,7 @@ for test in tests32e: grepstr="All tests ran without failures") configs.append(tc) -tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64f_divsqrt", "arch64d_divsqrt", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "arch64zfh", "arch64zfh_divsqrt", "arch64zfh_fma", "arch64zfaf", "arch64zfad", +tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64f_divsqrt", "arch64d_divsqrt", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "arch64zfh", "arch64zfh_divsqrt", "arch64zfh_fma", "arch64zfaf", "arch64zfad", "arch64zbkb", "arch64zbkc", "arch64zbkx", "arch64zknd", "arch64zkne", "arch64zknh", "arch64priv", "arch64c", "arch64m", "arch64a", "arch64zifencei", "arch64zicond", "wally64a", "wally64periph", "wally64priv"] # add arch64zfh_fma when available; arch64zicobz, arch64zcb when working #tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", # "arch64priv", "arch64c", "arch64m", "arch64a", "arch64zifencei", "wally64a", "wally64periph", "wally64priv", "arch64zicboz", "arch64zcb"] diff --git a/src/cvw.sv b/src/cvw.sv index 4defa196a..21b55c55e 100644 --- a/src/cvw.sv +++ b/src/cvw.sv @@ -187,8 +187,7 @@ typedef struct packed { logic ZKND_SUPPORTED; logic ZKNE_SUPPORTED; logic ZKNH_SUPPORTED; - logic ZKSED_SUPPORTED; - logic ZKSH_SUPPORTED; + logic ZK_SUPPORTED; // Memory synthesis configuration logic USE_SRAM; @@ -224,6 +223,7 @@ typedef struct packed { logic E_SUPPORTED; logic F_SUPPORTED; logic I_SUPPORTED; + logic K_SUPPORTED; logic M_SUPPORTED; logic Q_SUPPORTED; logic S_SUPPORTED; diff --git a/src/ieu/aes_common/aes_inv_shiftrow.sv b/src/ieu/aes_common/aes_inv_shiftrow.sv index 5b417f78f..be7f106b6 100644 --- a/src/ieu/aes_common/aes_inv_shiftrow.sv +++ b/src/ieu/aes_common/aes_inv_shiftrow.sv @@ -27,33 +27,40 @@ module aes_Inv_shiftrow(input logic [127:0] DataIn, output logic [127:0] DataOut); - + + logic [7:0] w0_b0, w0_b1, w0_b2, w0_b3; + logic [7:0] w1_b0, w1_b1, w1_b2, w1_b3; + logic [7:0] w2_b0, w2_b1, w2_b2, w2_b3; + logic [7:0] w3_b0, w3_b1, w3_b2, w3_b3; + logic [31:0] out_w0, out_w1, out_w2, out_w3; + // Separate the first (Least Significant) word into bytes - logic [7:0] w0_b0 = DataIn[7:0]; - logic [7:0] w0_b1 = DataIn[15:8]; - logic [7:0] w0_b2 = DataIn[23:16]; - logic [7:0] w0_b3 = DataIn[31:24]; + assign w0_b0 = DataIn[7:0]; + assign w0_b1 = DataIn[15:8]; + assign w0_b2 = DataIn[23:16]; + assign w0_b3 = DataIn[31:24]; // Separate the second word into bytes - logic [7:0] w1_b0 = DataIn[39:32]; - logic [7:0] w1_b1 = DataIn[47:40]; - logic [7:0] w1_b2 = DataIn[55:48]; - logic [7:0] w1_b3 = DataIn[63:56]; + assign w1_b0 = DataIn[39:32]; + assign w1_b1 = DataIn[47:40]; + assign w1_b2 = DataIn[55:48]; + assign w1_b3 = DataIn[63:56]; // Separate the third word into bytes - logic [7:0] w2_b0 = DataIn[71:64]; - logic [7:0] w2_b1 = DataIn[79:72]; - logic [7:0] w2_b2 = DataIn[87:80]; - logic [7:0] w2_b3 = DataIn[95:88]; + assign w2_b0 = DataIn[71:64]; + assign w2_b1 = DataIn[79:72]; + assign w2_b2 = DataIn[87:80]; + assign w2_b3 = DataIn[95:88]; // Separate the fourth (Most significant) word into bytes - logic [7:0] w3_b0 = DataIn[103:96]; - logic [7:0] w3_b1 = DataIn[111:104]; - logic [7:0] w3_b2 = DataIn[119:112]; - logic [7:0] w3_b3 = DataIn[127:120]; + assign w3_b0 = DataIn[103:96]; + assign w3_b1 = DataIn[111:104]; + assign w3_b2 = DataIn[119:112]; + assign w3_b3 = DataIn[127:120]; // The output words are composed of sets of the input bytes. - logic [31:0] out_w0 = {w0_b3, w1_b2, w2_b1, w3_b0}; - logic [31:0] out_w1 = {w3_b3, w0_b2, w1_b1, w2_b0}; - logic [31:0] out_w2 = {w2_b3, w3_b2, w0_b1, w1_b0}; - logic [31:0] out_w3 = {w1_b3, w2_b2, w3_b1, w0_b0}; + assign out_w0 = {w0_b3, w1_b2, w2_b1, w3_b0}; + assign out_w1 = {w3_b3, w0_b2, w1_b1, w2_b0}; + assign out_w2 = {w2_b3, w3_b2, w0_b1, w1_b0}; + assign out_w3 = {w1_b3, w2_b2, w3_b1, w0_b0}; assign DataOut = {out_w0, out_w1, out_w2, out_w3}; + endmodule diff --git a/src/ieu/aes_common/aes_shiftrow.sv b/src/ieu/aes_common/aes_shiftrow.sv index 4206b7a01..0344d7e21 100644 --- a/src/ieu/aes_common/aes_shiftrow.sv +++ b/src/ieu/aes_common/aes_shiftrow.sv @@ -31,31 +31,37 @@ module aes_shiftrow(input logic [127:0] DataIn, // (This form of writing it may seem like more effort but I feel // like it is more self-explanatory this way without losing efficiency) + logic [7:0] w0_b0, w0_b1, w0_b2, w0_b3; + logic [7:0] w1_b0, w1_b1, w1_b2, w1_b3; + logic [7:0] w2_b0, w2_b1, w2_b2, w2_b3; + logic [7:0] w3_b0, w3_b1, w3_b2, w3_b3; + logic [31:0] out_w0, out_w1, out_w2, out_w3; + // Seperate the first (Least Significant) word into bytes - logic [7:0] w0_b0 = DataIn[7:0]; - logic [7:0] w0_b1 = DataIn[79:72]; - logic [7:0] w0_b2 = DataIn[23:16]; - logic [7:0] w0_b3 = DataIn[95:88]; + assign w0_b0 = DataIn[7:0]; + assign w0_b1 = DataIn[79:72]; + assign w0_b2 = DataIn[23:16]; + assign w0_b3 = DataIn[95:88]; // Seperate the second word into bytes - logic [7:0] w1_b0 = DataIn[39:32]; - logic [7:0] w1_b1 = DataIn[111:104]; - logic [7:0] w1_b2 = DataIn[55:48]; - logic [7:0] w1_b3 = DataIn[127:120]; + assign w1_b0 = DataIn[39:32]; + assign w1_b1 = DataIn[111:104]; + assign w1_b2 = DataIn[55:48]; + assign w1_b3 = DataIn[127:120]; // Seperate the third word into bytes - logic [7:0] w2_b0 = DataIn[71:64]; - logic [7:0] w2_b1 = DataIn[15:8]; - logic [7:0] w2_b2 = DataIn[87:80]; - logic [7:0] w2_b3 = DataIn[31:24]; + assign w2_b0 = DataIn[71:64]; + assign w2_b1 = DataIn[15:8]; + assign w2_b2 = DataIn[87:80]; + assign w2_b3 = DataIn[31:24]; // Seperate the fourth (Most significant) word into bytes - logic [7:0] w3_b0 = DataIn[103:96]; - logic [7:0] w3_b1 = DataIn[47:40]; - logic [7:0] w3_b2 = DataIn[119:112]; - logic [7:0] w3_b3 = DataIn[63:56]; + assign w3_b0 = DataIn[103:96]; + assign w3_b1 = DataIn[47:40]; + assign w3_b2 = DataIn[119:112]; + assign w3_b3 = DataIn[63:56]; // The output words are composed of sets of the input bytes. - logic [31:0] out_w0 = {w0_b3, w1_b2, w2_b1, w3_b0}; - logic [31:0] out_w1 = {w3_b3, w0_b2, w1_b1, w2_b0}; - logic [31:0] out_w2 = {w2_b3, w3_b2, w0_b1, w1_b0}; - logic [31:0] out_w3 = {w1_b3, w2_b2, w3_b1, w0_b0}; + assign out_w0 = {w0_b3, w1_b2, w2_b1, w3_b0}; + assign out_w1 = {w3_b3, w0_b2, w1_b1, w2_b0}; + assign out_w2 = {w2_b3, w3_b2, w0_b1, w1_b0}; + assign out_w3 = {w1_b3, w2_b2, w3_b1, w0_b0}; assign DataOut = {out_w0, out_w1, out_w2, out_w3}; diff --git a/src/ieu/aes_instructions/aes32dsi.sv b/src/ieu/aes_instructions/aes32dsi.sv index 016cce1f1..58fc88c51 100644 --- a/src/ieu/aes_instructions/aes32dsi.sv +++ b/src/ieu/aes_instructions/aes32dsi.sv @@ -46,13 +46,14 @@ module aes32dsi(input logic [1:0] bs, assign Sbox_In = Sbox_In_32[7:0]; // Apply inverse sbox to si - aes_inv_sbox inv_sbox(.in(Sbox_In), .out(Sbox_Out)); + aes_Inv_sbox inv_sbox(.in(Sbox_In), .out(Sbox_Out)); // Pad output of inverse substitution box assign so = {24'h0, Sbox_Out}; // Rotate the substitution box output left by shamt (bs * 8) - rotate_left rol32(.input_data(so), .shamt(shamt), .rot_data(so_rotate)); + // rotate_left rol32(.input_data(so), .shamt(shamt), .rot_data(so_rotate)); + assign so_rotate = (so << shamt) | (so >> (32 - shamt)); // Set result to "X(rs1)[31..0] ^ rol32(so, unsigned(shamt));" assign Data_Out = rs1 ^ so_rotate; diff --git a/src/ieu/aes_instructions/aes32dsmi.sv b/src/ieu/aes_instructions/aes32dsmi.sv index 7db429c9d..df2bad83e 100644 --- a/src/ieu/aes_instructions/aes32dsmi.sv +++ b/src/ieu/aes_instructions/aes32dsmi.sv @@ -47,7 +47,7 @@ module aes32dsmi(input logic [1:0] bs, assign Sbox_In = Sbox_In_32[7:0]; // Apply inverse sbox to si - aes_inv_sbox inv_sbox(.in(Sbox_In), .out(Sbox_Out)); + aes_Inv_sbox inv_sbox(.in(Sbox_In), .out(Sbox_Out)); // Pad output of inverse substitution box assign so = {24'h0, Sbox_Out}; @@ -56,7 +56,8 @@ module aes32dsmi(input logic [1:0] bs, inv_mixword mix(.word(so), .mixed_word(mixed)); // Rotate the substitution box output left by shamt (bs * 8) - rotate_left rol32(.input_data(mixed), .shamt(shamt), .rot_data(mixed_rotate)); + // rotate_left rol32(.input_data(mixed), .shamt(shamt), .rot_data(mixed_rotate)); + assign mixed_rotate = (mixed << shamt) | (mixed >> (32 - shamt)); // Set result to "X(rs1)[31..0] ^ rol32(so, unsigned(shamt));" assign Data_Out = rs1 ^ mixed_rotate; diff --git a/src/ieu/aes_instructions/aes32esi.sv b/src/ieu/aes_instructions/aes32esi.sv index c34caa062..ed47e1d9d 100644 --- a/src/ieu/aes_instructions/aes32esi.sv +++ b/src/ieu/aes_instructions/aes32esi.sv @@ -54,7 +54,8 @@ module aes32esi(input logic [1:0] bs, assign so = {24'h0, Sbox_Out}; // Rotate so left by shamt - rotate_left rol32(.input_data(so), .shamt(shamt), .rot_data(so_rotate)); + // rotate_left rol32(.input_data(so), .shamt(shamt), .rot_data(so_rotate)); + assign so_rotate = (so << shamt) | (so >> (32 - shamt)); // Set result X(rs1)[31..0] ^ rol32(so, unsigned(shamt)); assign Data_Out = rs1 ^ so_rotate; diff --git a/src/ieu/aes_instructions/aes32esmi.sv b/src/ieu/aes_instructions/aes32esmi.sv index 25874b231..52d45c4de 100644 --- a/src/ieu/aes_instructions/aes32esmi.sv +++ b/src/ieu/aes_instructions/aes32esmi.sv @@ -58,7 +58,8 @@ module aes32esmi(input logic [1:0] bs, mixword mwd(.word(so), .mixed_word(mixed)); // Rotate so left by shamt - rotate_left rol32(.input_data(mixed), .shamt(shamt), .rot_data(mixed_rotate)); + // rotate_left rol32(.input_data(mixed), .shamt(shamt), .rot_data(mixed_rotate)); + assign mixed_rotate = (mixed << shamt) | (mixed >> (32 - shamt)); // Set result X(rs1)[31..0] ^ rol32(mixed, unsigned(shamt)); assign Data_Out = rs1 ^ mixed_rotate; diff --git a/src/ieu/aes_instructions/aes64ds.sv b/src/ieu/aes_instructions/aes64ds.sv index cb63fbf65..d1892675c 100644 --- a/src/ieu/aes_instructions/aes64ds.sv +++ b/src/ieu/aes_instructions/aes64ds.sv @@ -35,11 +35,11 @@ module aes64ds(input logic [63:0] rs1, logic [31:0] Sbox_Out_1; // Apply inverse shiftrows to rs2 and rs1 - aes_inv_shiftrow srow(.dataIn({rs2,rs1}), .dataOut(ShiftRow_Out)); + aes_Inv_shiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRow_Out)); // Apply full word inverse substitution to lower 2 words of shiftrow out - aes_inv_sbox_word inv_sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out_0)); - aes_inv_sbox_word inv_sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out_1)); + aes_Inv_sbox_word inv_sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out_0)); + aes_Inv_sbox_word inv_sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out_1)); // Concatenate the two substitution outputs to get result assign Data_Out = {Sbox_Out_1, Sbox_Out_0}; diff --git a/src/ieu/aes_instructions/aes64dsm.sv b/src/ieu/aes_instructions/aes64dsm.sv index 7ed85bcf3..241d718e2 100644 --- a/src/ieu/aes_instructions/aes64dsm.sv +++ b/src/ieu/aes_instructions/aes64dsm.sv @@ -37,11 +37,11 @@ module aes64dsm(input logic [63:0] rs1, logic [31:0] Mixcol_Out_1; // Apply inverse shiftrows to rs2 and rs1 - aes_inv_shiftrow srow(.dataIn({rs2, rs1}), .dataOut(ShiftRow_Out)); + aes_Inv_shiftrow srow(.DataIn({rs2, rs1}), .DataOut(ShiftRow_Out)); // Apply full word inverse substitution to lower 2 words of shiftrow out - aes_inv_sbox_word inv_sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out_0)); - aes_inv_sbox_word inv_sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out_1)); + aes_Inv_sbox_word inv_sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out_0)); + aes_Inv_sbox_word inv_sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out_1)); // Apply inverse mixword to sbox outputs inv_mixword inv_mw_0(.word(Sbox_Out_0), .mixed_word(Mixcol_Out_0)); diff --git a/src/ieu/aes_instructions/aes64es.sv b/src/ieu/aes_instructions/aes64es.sv index 97db8e443..58e6dfdc0 100644 --- a/src/ieu/aes_instructions/aes64es.sv +++ b/src/ieu/aes_instructions/aes64es.sv @@ -33,7 +33,7 @@ module aes64es(input logic [63:0] rs1, logic [127:0] ShiftRow_Out; // AES shiftrow unit - aes_shiftrow srow(.dataIn({rs2,rs1}), .dataOut(ShiftRow_Out)); + aes_shiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRow_Out)); // Apply substitution box to 2 lower words aes_sbox_word sbox_0(.in(ShiftRow_Out[31:0]), .out(Data_Out[31:0])); diff --git a/src/ieu/aes_instructions/aes64esm.sv b/src/ieu/aes_instructions/aes64esm.sv index be73d87dc..80c8f34d6 100644 --- a/src/ieu/aes_instructions/aes64esm.sv +++ b/src/ieu/aes_instructions/aes64esm.sv @@ -34,7 +34,7 @@ module aes64esm(input logic [63:0] rs1, logic [63:0] Sbox_Out; // AES shiftrow unit - aes_shiftrow srow(.dataIn({rs2,rs1}), .dataOut(ShiftRow_Out)); + aes_shiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRow_Out)); // Apply substitution box to 2 lower words aes_sbox_word sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out[31:0])); diff --git a/src/ieu/aes_instructions/aes64ks1i.sv b/src/ieu/aes_instructions/aes64ks1i.sv index 4738bb747..5ef76516c 100644 --- a/src/ieu/aes_instructions/aes64ks1i.sv +++ b/src/ieu/aes_instructions/aes64ks1i.sv @@ -58,63 +58,3 @@ module aes64ks1i(input logic [3:0] roundnum, endmodule -module rcon_lut_128(input logic [3:0] RD, - output logic [7:0] rcon_out); - - always_comb - begin - case(RD) - 4'h0 : rcon_out = 8'h01; - 4'h1 : rcon_out = 8'h02; - 4'h2 : rcon_out = 8'h04; - 4'h3 : rcon_out = 8'h08; - 4'h4 : rcon_out = 8'h10; - 4'h5 : rcon_out = 8'h20; - 4'h6 : rcon_out = 8'h40; - 4'h7 : rcon_out = 8'h80; - 4'h8 : rcon_out = 8'h1b; - 4'h9 : rcon_out = 8'h36; - 4'hA : rcon_out = 8'h00; - default : rcon_out = 8'h00; - endcase - end - -endmodule - -module rrot8(input logic[31:0] x, - output logic [31:0] result); - - assign result[0] = x[8]; - assign result[1] = x[9]; - assign result[2] = x[10]; - assign result[3] = x[11]; - assign result[4] = x[12]; - assign result[5] = x[13]; - assign result[6] = x[14]; - assign result[7] = x[15]; - assign result[8] = x[16]; - assign result[9] = x[17]; - assign result[10] = x[18]; - assign result[11] = x[19]; - assign result[12] = x[20]; - assign result[13] = x[21]; - assign result[14] = x[22]; - assign result[15] = x[23]; - assign result[16] = x[24]; - assign result[17] = x[25]; - assign result[18] = x[26]; - assign result[19] = x[27]; - assign result[20] = x[28]; - assign result[21] = x[29]; - assign result[22] = x[30]; - assign result[23] = x[31]; - assign result[24] = x[0]; - assign result[25] = x[1]; - assign result[26] = x[2]; - assign result[27] = x[3]; - assign result[28] = x[4]; - assign result[29] = x[5]; - assign result[30] = x[6]; - assign result[31] = x[7]; - -endmodule diff --git a/src/ieu/kmu/packer.sv b/src/ieu/kmu/packer.sv index 42702d89c..1e0c3f542 100644 --- a/src/ieu/kmu/packer.sv +++ b/src/ieu/kmu/packer.sv @@ -30,38 +30,30 @@ module packer #(parameter WIDTH=32) ( input logic [2:0] PackSelect, output logic [WIDTH-1:0] PackResult); - logic [WIDTH/2-1:0] low_half, high_half; - logic [7:0] low_halfh, high_halfh; - logic [15:0] low_halfw, high_halfw; + logic [WIDTH/2-1:0] low_half, high_half; + logic [7:0] low_halfh, high_halfh; + logic [15:0] low_halfw, high_halfw; + + logic [WIDTH-1:0] Pack; + logic [WIDTH-1:0] PackH; + logic [WIDTH-1:0] PackW; - logic [WIDTH-1:0] Pack; - logic [WIDTH-1:0] PackH; - logic [WIDTH-1:0] PackW; - logic [1:0] MuxSelect; - - assign low_half = A[WIDTH/2-1:0]; - assign high_half = B[WIDTH/2-1:0]; - assign low_halfh = A[7:0]; - assign high_halfh = B[7:0]; - assign low_halfw = A[15:0]; - assign high_halfw = B[15:0]; - - assign Pack = {high_half, low_half}; - assign PackH = {{(WIDTH-16){1'b0}}, high_halfh, low_halfh}; - assign PackW = {{(WIDTH-32){high_halfw[15]}}, high_halfw, low_halfw}; - - // TODO: FIX THIS ... this is completely incorrect way to use if statements - // Solution for now: - always_comb - begin - if (PackSelect[1:0] == 2'b11) - MuxSelect = 2'b01; - else if (PackSelect[2] == 1'b0) - MuxSelect = 2'b00; - else - MuxSelect = 2'b10; - end - - mux3 #(WIDTH) PackMux(Pack, PackH, PackW, MuxSelect, PackResult); + assign low_half = A[WIDTH/2-1:0]; + assign high_half = B[WIDTH/2-1:0]; + assign low_halfh = A[7:0]; + assign high_halfh = B[7:0]; + assign low_halfw = A[15:0]; + assign high_halfw = B[15:0]; + + assign Pack = {high_half, low_half}; + assign PackH = {{(WIDTH-16){1'b0}}, high_halfh, low_halfh}; + assign PackW = {{(WIDTH-32){high_halfw[15]}}, high_halfw, low_halfw}; + + always_comb + begin + if (PackSelect[1:0] == 2'b11) PackResult = PackH; + else if (PackSelect[2] == 1'b0) PackResult = Pack; + else PackResult = PackW; + end endmodule diff --git a/src/ieu/kmu/zknd_32.sv b/src/ieu/kmu/zknd_32.sv index 6ef6da9a9..2b36fe0df 100644 --- a/src/ieu/kmu/zknd_32.sv +++ b/src/ieu/kmu/zknd_32.sv @@ -36,8 +36,8 @@ module zknd_32 #(parameter WIDTH=32) logic [31:0] aes32dsmiRes; // RV32 - aes32dsi aes32dsi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .data_out(aes32dsiRes)); - aes32dsmi aes32dsmi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .data_out(aes32dsmiRes)); + aes32dsi aes32dsi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .Data_Out(aes32dsiRes)); + aes32dsmi aes32dsmi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .Data_Out(aes32dsmiRes)); mux2 #(WIDTH) zkndmux (aes32dsiRes, aes32dsmiRes, ZKNDSelect[0], ZKNDResult); diff --git a/src/ieu/kmu/zknd_64.sv b/src/ieu/kmu/zknd_64.sv index 69e190ad3..0bc4cf16a 100644 --- a/src/ieu/kmu/zknd_64.sv +++ b/src/ieu/kmu/zknd_64.sv @@ -40,9 +40,9 @@ module zknd_64 #(parameter WIDTH=32) logic [63:0] aes64ks2Res; // RV64 - aes64ds aes64ds (.rs1(A), .rs2(B), .data_out(aes64dsRes)); - aes64dsm aes64dsm (.rs1(A), .rs2(B), .data_out(aes64dsmRes)); - aes64im aes64im (.rs1(A), .data_out(aes64imRes)); + aes64ds aes64ds (.rs1(A), .rs2(B), .Data_Out(aes64dsRes)); + aes64dsm aes64dsm (.rs1(A), .rs2(B), .Data_Out(aes64dsmRes)); + aes64im aes64im (.rs1(A), .Data_Out(aes64imRes)); aes64ks1i aes64ks1i (.roundnum(RNUM), .rs1(A), .rd(aes64ks1iRes)); aes64ks2 aes64ks2 (.rs2(B), .rs1(A), .rd(aes64ks2Res)); diff --git a/src/ieu/kmu/zkne_32.sv b/src/ieu/kmu/zkne_32.sv index c4ec0b78d..273453184 100644 --- a/src/ieu/kmu/zkne_32.sv +++ b/src/ieu/kmu/zkne_32.sv @@ -36,8 +36,8 @@ module zkne_32 #(parameter WIDTH=32) logic [31:0] aes32esmiRes; // RV32 - aes32esi aes32esi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .data_out(aes32esiRes)); - aes32esmi aes32esmi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .data_out(aes32esmiRes)); + aes32esi aes32esi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .Data_Out(aes32esiRes)); + aes32esmi aes32esmi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .Data_Out(aes32esmiRes)); mux2 #(WIDTH) zknemux (aes32esiRes, aes32esmiRes, ZKNESelect[0], ZKNEResult); diff --git a/src/ieu/kmu/zkne_64.sv b/src/ieu/kmu/zkne_64.sv index 84e45852f..1961f025e 100644 --- a/src/ieu/kmu/zkne_64.sv +++ b/src/ieu/kmu/zkne_64.sv @@ -39,8 +39,8 @@ module zkne_64 #(parameter WIDTH=32) logic [63:0] aes64ks2Res; // RV64 - aes64es aes64es (.rs1(A), .rs2(B), .data_out(aes64esRes)); - aes64esm aes64esm (.rs1(A), .rs2(B), .data_out(aes64esmRes)); + aes64es aes64es (.rs1(A), .rs2(B), .Data_Out(aes64esRes)); + aes64esm aes64esm (.rs1(A), .rs2(B), .Data_Out(aes64esmRes)); aes64ks1i aes64ks1i (.roundnum(RNUM), .rs1(A), .rd(aes64ks1iRes)); aes64ks2 aes64ks2 (.rs2(B), .rs1(A), .rd(aes64ks2Res)); diff --git a/testbench/common/instrNameDecTB.sv b/testbench/common/instrNameDecTB.sv index ee6cd6900..3c702ffd5 100644 --- a/testbench/common/instrNameDecTB.sv +++ b/testbench/common/instrNameDecTB.sv @@ -58,6 +58,17 @@ module instrNameDecTB( else if (funct7[6:1] == 6'b010010) name = "BCLRI"; else if (funct7[6:1] == 6'b011010) name = "BINVI"; else if (funct7[6:1] == 6'b001010) name = "BSETI"; + else if (funct7 == 7'b0000100 && rs2 == 5'b01111) name = "ZIP"; + else if (funct7 == 7'b0011000 && rs2 == 5'b00000) name = "AES64IM"; + else if (funct7 == 7'b0011000 && rs2[4] == 1'b1) name = "AES64KS1I"; + else if (funct7 == 7'b0001000 && rs2 == 5'b00010) name = "SHA256SIG0"; + else if (funct7 == 7'b0001000 && rs2 == 5'b00011) name = "SHA256SIG1"; + else if (funct7 == 7'b0001000 && rs2 == 5'b00000) name = "SHA256SUM0"; + else if (funct7 == 7'b0001000 && rs2 == 5'b00001) name = "SHA256SUM1"; + else if (funct7 == 7'b0001000 && rs2 == 5'b00110) name = "SHA512SIG0"; + else if (funct7 == 7'b0001000 && rs2 == 5'b00111) name = "SHA512SIG1"; + else if (funct7 == 7'b0001000 && rs2 == 5'b00100) name = "SHA512SUM0"; + else if (funct7 == 7'b0001000 && rs2 == 5'b00101) name = "SHA512SUM1"; else if (funct7 == 7'b0110000) begin case (rs2) 5'b00000: name = "CLZ"; @@ -77,6 +88,8 @@ module instrNameDecTB( else if (funct7[6:1] == 6'b011000) name = "RORI"; else if (funct7[6:1] == 6'b010010) name = "BEXTI"; else if (funct7 == 7'b0010100 & rs2 == 5'b00111) name = "ORC.B"; + else if (imm == 12'b011010000111) name = "BREV8"; + else if (funct7 == 7'b0000100 && rs2 == 5'b01111) name = "UNZIP"; else name = "ILLEGAL"; 10'b0010011_110: if (rd == 0 & rs2 == 0) name = "PREFETCH.I"; else if (rd == 0 & rs2 == 1) name = "PREFETCH.R"; @@ -130,6 +143,21 @@ module instrNameDecTB( 10'b0110011_000: if (funct7 == 7'b0000000) name = "ADD"; else if (funct7 == 7'b0000001) name = "MUL"; else if (funct7 == 7'b0100000) name = "SUB"; + else if (funct7[4:0] == 5'b10101) name = "AES32DSI"; + else if (funct7[4:0] == 5'b10111) name = "AES32DSMI"; + else if (funct7 == 7'b0011101) name = "AES64DS"; + else if (funct7 == 7'b0011111) name = "AES64DSM"; + else if (funct7[4:0] == 5'b10001) name = "AES32ESI"; + else if (funct7[4:0] == 5'b10011) name = "AES32ESMI"; + else if (funct7 == 7'b0011001) name = "AES64ES"; + else if (funct7 == 7'b0011011) name = "AES64ESM"; + else if (funct7 == 7'b0111111) name = "AES64KS2"; + else if (funct7 == 7'b0101110) name = "SHA512SIG0H"; + else if (funct7 == 7'b0101010) name = "SHA512SIG0L"; + else if (funct7 == 7'b0101111) name = "SHA512SIG1H"; + else if (funct7 == 7'b0101011) name = "SHA512SIG1L"; + else if (funct7 == 7'b0101000) name = "SHA512SUM0R"; + else if (funct7 == 7'b0101001) name = "SHA512SUM1R"; else name = "ILLEGAL"; 10'b0110011_001: if (funct7 == 7'b0000000) name = "SLL"; else if (funct7 == 7'b0000001) name = "MULH"; @@ -153,7 +181,9 @@ module instrNameDecTB( else if (funct7 == 7'b0010000) name = "SH2ADD"; else if (funct7 == 7'b0000101) name = "MIN"; else if (funct7 == 7'b0100000) name = "ORN"; - else if (funct7 == 7'b0000100) name = "ZEXT.H"; + else if (funct7 == 7'b0000100 && rs2 == 5'b00000) name = "ZEXT.H"; + else if (funct7 == 7'b0000100 && op == 7'b0110011) name = "PACK"; + else if (funct7 == 7'b0000100 && op == 7'b0111011) name = "PACKW"; else name = "ILLEGAL"; 10'b0110011_101: if (funct7 == 7'b0000000) name = "SRL"; else if (funct7 == 7'b0000001) name = "DIVU"; diff --git a/testbench/testbench-xcelium.sv b/testbench/testbench-xcelium.sv index 44afbcd3b..68d0ff3ef 100644 --- a/testbench/testbench-xcelium.sv +++ b/testbench/testbench-xcelium.sv @@ -129,6 +129,12 @@ module testbench; "arch64zbb": if (P.ZBB_SUPPORTED) tests = arch64zbb; "arch64zbc": if (P.ZBC_SUPPORTED) tests = arch64zbc; "arch64zbs": if (P.ZBS_SUPPORTED) tests = arch64zbs; + "arch64zbkb": if (P.ZBKB_SUPPORTED) tests = arch64zbkb; + "arch64zbkc": if (P.ZBKC_SUPPORTED) tests = arch64zbkc; + "arch64zbkx": if (P.ZBKX_SUPPORTED) tests = arch64zbkx; + "arch64zknd": if (P.ZKND_SUPPORTED) tests = arch64zknd; + "arch64zkne": if (P.ZKNE_SUPPORTED) tests = arch64zkne; + "arch64zknh": if (P.ZKNH_SUPPORTED) tests = arch64zknh; endcase end else begin // RV32 case (TEST) @@ -159,6 +165,12 @@ module testbench; "arch32zbb": if (P.ZBB_SUPPORTED) tests = arch32zbb; "arch32zbc": if (P.ZBC_SUPPORTED) tests = arch32zbc; "arch32zbs": if (P.ZBS_SUPPORTED) tests = arch32zbs; + "arch32zbkb": if (P.ZBKB_SUPPORTED) tests = arch32zbkb; + "arch32zbkc": if (P.ZBKC_SUPPORTED) tests = arch32zbkc; + "arch32zbkx": if (P.ZBKX_SUPPORTED) tests = arch32zbkx; + "arch32zknd": if (P.ZKND_SUPPORTED) tests = arch32zknd; + "arch32zkne": if (P.ZKNE_SUPPORTED) tests = arch32zkne; + "arch32zknh": if (P.ZKNH_SUPPORTED) tests = arch32zknh; endcase end if (tests.size() == 0) begin diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 0f8194e62..036447341 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -147,6 +147,12 @@ module testbench; "arch64zfaf": if (P.ZFA_SUPPORTED) tests = arch64zfaf; "arch64zfad": if (P.ZFA_SUPPORTED & P.D_SUPPORTED) tests = arch64zfad; "buildroot": tests = buildroot; + "arch64zbkb": if (P.ZBKB_SUPPORTED) tests = arch64zbkb; + "arch64zbkc": if (P.ZBKC_SUPPORTED) tests = arch64zbkc; + "arch64zbkx": if (P.ZBKX_SUPPORTED) tests = arch64zbkx; + "arch64zknd": if (P.ZKND_SUPPORTED) tests = arch64zknd; + "arch64zkne": if (P.ZKNE_SUPPORTED) tests = arch64zkne; + "arch64zknh": if (P.ZKNH_SUPPORTED) tests = arch64zknh; endcase end else begin // RV32 case (TEST) @@ -189,6 +195,12 @@ module testbench; "arch32zfh_divsqrt": if (P.ZFH_SUPPORTED) tests = arch32zfh_divsqrt; "arch32zfaf": if (P.ZFA_SUPPORTED) tests = arch32zfaf; "arch32zfad": if (P.ZFA_SUPPORTED & P.D_SUPPORTED) tests = arch32zfad; + "arch32zbkb": if (P.ZBKB_SUPPORTED) tests = arch32zbkb; + "arch32zbkc": if (P.ZBKC_SUPPORTED) tests = arch32zbkc; + "arch32zbkx": if (P.ZBKX_SUPPORTED) tests = arch32zbkx; + "arch32zknd": if (P.ZKND_SUPPORTED) tests = arch32zknd; + "arch32zkne": if (P.ZKNE_SUPPORTED) tests = arch32zkne; + "arch32zknh": if (P.ZKNH_SUPPORTED) tests = arch32zknh; endcase end if (tests.size() == 0) begin diff --git a/testbench/tests.vh b/testbench/tests.vh index 95ebb74b3..fc04e9f7b 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -990,6 +990,53 @@ string imperas32f[] = '{ "rv32i_m/B/src/bseti-01.S" }; + string arch32zbkb[] = '{ + `RISCVARCHTEST, + "rv32i_m/K/src/brev8_32-01.S", + "rv32i_m/K/src/pack-01.S", + "rv32i_m/K/src/packh-01.S", + "rv32i_m/K/src/unzip-01.S", + "rv32i_m/K/src/zip-01.S" + }; + + string arch32zbkc[] = '{ + `RISCVARCHTEST, + "rv32i_m/B/src/clmul-01.S", + "rv32i_m/B/src/clmulh-01.S" + }; + + string arch32zbkx[] = '{ + `RISCVARCHTEST, + "rv32i_m/K/src/xperm8-01.S", + "rv32i_m/K/src/xperm4-01.S" + }; + + string arch32zknd[] = '{ + `RISCVARCHTEST, + "rv32i_m/K/src/aes32dsi-01.S", + "rv32i_m/K/src/aes32dsmi-01.S" + }; + + string arch32zkne[] = '{ + `RISCVARCHTEST, + "rv32i_m/K/src/aes32esi-01.S", + "rv32i_m/K/src/aes32esmi-01.S" + }; + + string arch32zknh[] = '{ + `RISCVARCHTEST, + "rv32i_m/K/src/sha256sig0-01.S", + "rv32i_m/K/src/sha256sig1-01.S", + "rv32i_m/K/src/sha256sum0-01.S", + "rv32i_m/K/src/sha256sum1-01.S", + "rv32i_m/K/src/sha512sig0h-01.S", + "rv32i_m/K/src/sha512sig0l-01.S", + "rv32i_m/K/src/sha512sig1h-01.S", + "rv32i_m/K/src/sha512sig1l-01.S", + "rv32i_m/K/src/sha512sum0r-01.S", + "rv32i_m/K/src/sha512sum1r-01.S" + }; + string arch64m[] = '{ `RISCVARCHTEST, "rv64i_m/M/src/div-01.S", @@ -1748,6 +1795,55 @@ string arch64zbs[] = '{ "rv64i_m/B/src/bseti-01.S" }; +string arch64zbkb[] = '{ + `RISCVARCHTEST, + "rv64i_m/K/src/brev8-01.S", + "rv64i_m/K/src/pack-01.S", + "rv64i_m/K/src/packh-01.S", + "rv64i_m/K/src/packw-01.S" +}; + +string arch64zbkc[] = '{ + `RISCVARCHTEST, + "rv64i_m/B/src/clmul-01.S", + "rv64i_m/B/src/clmulh-01.S" +}; + +string arch64zbkx[] = '{ + `RISCVARCHTEST, + "rv64i_m/K/src/xperm8-01.S", + "rv64i_m/K/src/xperm4-01.S" +}; + +string arch64zknd[] = '{ + `RISCVARCHTEST, + "rv64i_m/K/src/aes64ds-01.S", + "rv64i_m/K/src/aes64dsm-01.S", + "rv64i_m/K/src/aes64im-01.S", + "rv64i_m/K/src/aes64ks1i-01.S", + "rv64i_m/K/src/aes64ks2-01.S" +}; + +string arch64zkne[] = '{ + `RISCVARCHTEST, + "rv64i_m/K/src/aes64es-01.S", + "rv64i_m/K/src/aes64esm-01.S", + "rv64i_m/K/src/aes64ks1i-01.S", + "rv64i_m/K/src/aes64ks2-01.S" +}; + +string arch64zknh[] = '{ + `RISCVARCHTEST, + "rv64i_m/K/src/sha256sig0-01.S", + "rv64i_m/K/src/sha256sig1-01.S", + "rv64i_m/K/src/sha256sum0-01.S", + "rv64i_m/K/src/sha256sum1-01.S", + "rv64i_m/K/src/sha512sig0-01.S", + "rv64i_m/K/src/sha512sig1-01.S", + "rv64i_m/K/src/sha512sum0-01.S", + "rv64i_m/K/src/sha512sum1-01.S" +}; + string arch32priv[] = '{ `RISCVARCHTEST, "rv32i_m/privilege/src/ebreak.S", diff --git a/tests/riscof/spike/riscof_spike.py b/tests/riscof/spike/riscof_spike.py index 5450f64df..f5b8ea317 100644 --- a/tests/riscof/spike/riscof_spike.py +++ b/tests/riscof/spike/riscof_spike.py @@ -131,6 +131,18 @@ class spike(pluginTemplate): self.isa += '_Zbc' if "Zbs" in ispec["ISA"]: self.isa += '_Zbs' + if "Zbkb" in ispec["ISA"]: + self.isa += '_Zbkb' + if "Zbkc" in ispec["ISA"]: + self.isa += '_Zbkc' + if "Zknd" in ispec["ISA"]: + self.isa += '_Zknd' + if "Zkne" in ispec["ISA"]: + self.isa += '_Zkne' + if "Zbkx" in ispec["ISA"]: + self.isa += '_Zbkx' + if "Zknh" in ispec["ISA"]: + self.isa += '_Zknh' #TODO: The following assumes you are using the riscv-gcc toolchain. If # not please change appropriately diff --git a/tests/riscof/spike/spike_rv32e_isa.yaml b/tests/riscof/spike/spike_rv32e_isa.yaml index 9e9775a9b..ee0aeec11 100644 --- a/tests/riscof/spike/spike_rv32e_isa.yaml +++ b/tests/riscof/spike/spike_rv32e_isa.yaml @@ -1,6 +1,6 @@ hart_ids: [0] hart0: - ISA: RV32EMCZicsr_Zifencei + ISA: RV32EMCZicsr_Zifencei_Zbkc physical_addr_sz: 32 User_Spec_Version: '2.3' supported_xlen: [32] diff --git a/tests/riscof/spike/spike_rv32gc_isa.yaml b/tests/riscof/spike/spike_rv32gc_isa.yaml index d13420bba..1879440ed 100644 --- a/tests/riscof/spike/spike_rv32gc_isa.yaml +++ b/tests/riscof/spike/spike_rv32gc_isa.yaml @@ -1,6 +1,6 @@ hart_ids: [0] hart0: - ISA: RV32IMAFDCZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh + ISA: RV32IMAFDCZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh # ISA: RV32IMAFDCZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbs # ISA: RV32IMAFDCZicsr_Zicboz_Zifencei_Zca_Zba_Zbb_Zbc_Zbs # _Zbkb_Zcb physical_addr_sz: 32 diff --git a/tests/riscof/spike/spike_rv64gc_isa.yaml b/tests/riscof/spike/spike_rv64gc_isa.yaml index a40b579bd..6ee45513f 100644 --- a/tests/riscof/spike/spike_rv64gc_isa.yaml +++ b/tests/riscof/spike/spike_rv64gc_isa.yaml @@ -3,7 +3,7 @@ hart0: # ISA: RV64IMAFDCSUZicsr_Zicboz_Zifencei_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb # ISA: RV64IMAFDCSUZicsr_Zifencei_Zca_Zcb_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb # ISA: RV64IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb - ISA: RV64IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh + ISA: RV64IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh physical_addr_sz: 56 User_Spec_Version: '2.3' supported_xlen: [64]