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Cleanup.

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This commit is contained in:
Ross Thompson 2022-02-04 22:40:51 -06:00
parent 4074f695e0
commit 011ad09341
3 changed files with 3 additions and 5 deletions
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2
pipelined/src/ifu/ifu.sv
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@ -193,7 +193,7 @@ module ifu (
.LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusWrite(), .LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusWrite(),
.LSUBusRead(IFUBusRead), .LSUBusSize(), .LSUBusRead(IFUBusRead), .LSUBusSize(),
.LSUFunct3M(3'b010), .LSUBusAdr(IFUBusAdr), .DCacheBusAdr(ICacheBusAdr), .LSUFunct3M(3'b010), .LSUBusAdr(IFUBusAdr), .DCacheBusAdr(ICacheBusAdr),
.WordCount(), .SelUncachedAdr(), .LSUBusHWDATA(), .WordCount(), .LSUBusHWDATA(),
.ReadDataLineSetsM(), .DCacheFetchLine(ICacheFetchLine), .ReadDataLineSetsM(), .DCacheFetchLine(ICacheFetchLine),
.DCacheWriteLine(1'b0), .DCacheBusAck(ICacheBusAck), .DCacheWriteLine(1'b0), .DCacheBusAck(ICacheBusAck),
.DCacheMemWriteData(ICacheMemWriteData), .LSUPAdrM(PCPF), .DCacheMemWriteData(ICacheMemWriteData), .LSUPAdrM(PCPF),

3
pipelined/src/lsu/busdp.sv
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@ -47,7 +47,6 @@ module busdp #(parameter WORDSPERLINE, LINELEN, WORDLEN, LOGWPL, LSU=0)
input logic [2:0] LSUFunct3M, input logic [2:0] LSUFunct3M,
output logic [`PA_BITS-1:0] LSUBusAdr, output logic [`PA_BITS-1:0] LSUBusAdr,
output logic [LOGWPL-1:0] WordCount, output logic [LOGWPL-1:0] WordCount,
output logic SelUncachedAdr,
// cache interface. // cache interface.
input logic [`PA_BITS-1:0] DCacheBusAdr, input logic [`PA_BITS-1:0] DCacheBusAdr,
input var logic [`XLEN-1:0] ReadDataLineSetsM [WORDSPERLINE-1:0], input var logic [`XLEN-1:0] ReadDataLineSetsM [WORDSPERLINE-1:0],
@ -73,7 +72,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, WORDLEN, LOGWPL, LSU=0)
logic [`XLEN-1:0] PreLSUBusHWDATA; logic [`XLEN-1:0] PreLSUBusHWDATA;
logic [`PA_BITS-1:0] LocalLSUBusAdr; logic [`PA_BITS-1:0] LocalLSUBusAdr;
logic SelUncachedAdr;
genvar index; genvar index;
for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer

3
pipelined/src/lsu/lsu.sv
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@ -202,7 +202,7 @@ module lsu (
busdp #(WORDSPERLINE, LINELEN, `XLEN, LOGWPL, 1) busdp( busdp #(WORDSPERLINE, LINELEN, `XLEN, LOGWPL, 1) busdp(
.clk, .reset, .clk, .reset,
.LSUBusHRDATA, .LSUBusHWDATA, .LSUBusAck, .LSUBusWrite, .LSUBusRead, .LSUBusSize, .LSUBusHRDATA, .LSUBusHWDATA, .LSUBusAck, .LSUBusWrite, .LSUBusRead, .LSUBusSize,
.WordCount, .SelUncachedAdr, .WordCount,
.LSUFunct3M, .LSUBusAdr, .DCacheBusAdr, .ReadDataLineSetsM, .DCacheFetchLine, .LSUFunct3M, .LSUBusAdr, .DCacheBusAdr, .ReadDataLineSetsM, .DCacheFetchLine,
.DCacheWriteLine, .DCacheBusAck, .DCacheMemWriteData, .LSUPAdrM, .FinalAMOWriteDataM, .DCacheWriteLine, .DCacheBusAck, .DCacheMemWriteData, .LSUPAdrM, .FinalAMOWriteDataM,
.ReadDataWordM, .ReadDataWordMuxM, .IgnoreRequest, .LSURWM, .CPUBusy, .CacheableM, .ReadDataWordM, .ReadDataWordMuxM, .IgnoreRequest, .LSURWM, .CPUBusy, .CacheableM,
@ -211,7 +211,6 @@ module lsu (
assign Pad = '0; assign Pad = '0;
assign WordOffsetAddr = LSUBusWrite ? ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) : LSUPAdrM; assign WordOffsetAddr = LSUBusWrite ? ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) : LSUPAdrM;
subcachelineread #(LINELEN, `XLEN, `XLEN) subcachelineread( subcachelineread #(LINELEN, `XLEN, `XLEN) subcachelineread(
.clk, .reset, .PAdr(WordOffsetAddr), .save, .restore, .clk, .reset, .PAdr(WordOffsetAddr), .save, .restore,
.ReadDataLine(ReadDataLineM), .ReadDataWord(ReadDataWordM)); .ReadDataLine(ReadDataLineM), .ReadDataWord(ReadDataWordM));