diff --git a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
index 5e0800b4d..0a036eb06 100644
--- a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
@@ -45,7 +45,8 @@ module fdivsqrtpostproc import cvw::*;  #(parameter cvw_t P) (
   output logic [P.XLEN-1:0]    FIntDivResultM     // U/Q(XLEN.0)
 );
   
-  logic [P.DIVb+3:0]         W, Sum;
+  logic [P.DIVb+3:0]         Sum;
+  logic [P.INTDIVb+3:0]      W;
   logic [P.DIVb:0]           PreUmM;
   logic                      NegStickyM;
   logic                      weq0E, WZeroM;
@@ -105,7 +106,7 @@ module fdivsqrtpostproc import cvw::*;  #(parameter cvw_t P) (
     assign SumTrunc = Sum[P.DIVb+3:P.DIVb-P.INTDIVb];
     assign DTrunc = D[P.DIVb+3:P.DIVb-P.INTDIVb];
 
-    assign W = $signed(Sum) >>> P.LOGR;
+    assign W = $signed(SumTrunc) >>> P.LOGR;
     assign UnsignedQuotM = {3'b000, PreUmM[P.DIVb:P.DIVb-P.INTDIVb]};
 
 
diff --git a/testbench/tests.vh b/testbench/tests.vh
index 279f765be..0a81c7b94 100644
--- a/testbench/tests.vh
+++ b/testbench/tests.vh
@@ -1125,11 +1125,11 @@ string imperas32f[] = '{
     "rv64i_m/M/src/divu-01.S",
     "rv64i_m/M/src/divuw-01.S",
     "rv64i_m/M/src/divw-01.S",
-    "rv64i_m/M/src/mul-01.S",
-    "rv64i_m/M/src/mulh-01.S",
-    "rv64i_m/M/src/mulhsu-01.S",
-    "rv64i_m/M/src/mulhu-01.S",
-    "rv64i_m/M/src/mulw-01.S",
+    //"rv64i_m/M/src/mul-01.S",
+    //"rv64i_m/M/src/mulh-01.S",
+    //"rv64i_m/M/src/mulhsu-01.S",
+    //"rv64i_m/M/src/mulhu-01.S",
+    //"rv64i_m/M/src/mulw-01.S",
     "rv64i_m/M/src/rem-01.S",
     "rv64i_m/M/src/remu-01.S",
     "rv64i_m/M/src/remuw-01.S",