cvw/pipelined/src/generic/lzc.sv

16 lines
490 B
Systemverilog
Raw Normal View History

//leading zero counter i.e. priority encoder
module lzc #(parameter WIDTH=1) (
input logic [WIDTH-1:0] num,
2022-05-31 16:18:50 +00:00
output logic [$clog2(WIDTH+1)-1:0] ZeroCnt
);
2022-05-27 18:36:04 +00:00
/* verilator lint_off CMPCONST */
2022-05-31 16:18:50 +00:00
logic [$clog2(WIDTH+1)-1:0] i;
always_comb begin
i = 0;
2022-05-31 16:18:50 +00:00
while (~num[WIDTH-1-(32)'(i)] & $unsigned(i) <= $unsigned(($clog2(WIDTH+1))'(WIDTH-1))) i = i+1; // search for leading one
ZeroCnt = i;
end
2022-05-27 18:36:04 +00:00
/* verilator lint_on CMPCONST */
endmodule