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https://github.com/openhwgroup/cvw
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58 lines
1.9 KiB
Systemverilog
58 lines
1.9 KiB
Systemverilog
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///////////////////////////////////////////
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// satCounter2.sv
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//
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// Written: Ross Thomposn
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// Email: ross1728@gmail.com
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// Created: February 13, 2021
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// Modified:
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//
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// Purpose: 2 bit starting counter
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module satCounter2
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(input logic BrDir,
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input logic [1:0] OldState,
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output logic [1:0] NewState
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);
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always_comb begin
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case(OldState)
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2'b00: begin
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if(BrDir) NewState = 2'b01;
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else NewState = 2'b00;
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end
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2'b01: begin
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if(BrDir) NewState = 2'b10;
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else NewState = 2'b00;
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end
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2'b10: begin
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if(BrDir) NewState = 2'b11;
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else NewState = 2'b01;
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end
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2'b11: begin
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if(BrDir) NewState = 2'b11;
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else NewState = 2'b10;
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end
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endcase
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end
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endmodule
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