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https://github.com/openhwgroup/cvw
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37 lines
1.6 KiB
Systemverilog
37 lines
1.6 KiB
Systemverilog
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///////////////////////////////////////////
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// prioritythermometer.sv
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//
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// Written: ross1728@gmail.com November 14, 2022
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//
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// Purpose: one-hot to binary encoding.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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module binencoder #(parameter N = 8) (
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input logic [N-1:0] A,
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output logic [$clog2(N)-1:0] Y);
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integer index;
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always_comb begin
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Y = 0;
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for(index = 0; index < N; index++)
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if(A[index] == 1'b1) Y = index[$clog2(N)-1:0];
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end
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endmodule
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