cvw/pipelined/regression/wally-pipelined-fpga.do

# wally-pipelined.do 
#
# Modification by Oklahoma State University & Harvey Mudd College
# Use with Testbench 
# James Stine, 2008; David Harris 2021
# Go Cowboys!!!!!!
#
# Takes 1:10 to run RV64IC tests using gui

# Use this wally-pipelined.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
#     do wally-pipelined.do
# or, to run from a shell, type the following at the shell prompt:
#     vsim -do wally-pipelined.do -c
# (omit the "-c" to see the GUI while running from the shell)

onbreak {resume}

# create library
if [file exists work] {
    vdel -all
}
vlib work

# compile source files
# suppress spurious warnngs about 
# "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt

# default to config/rv64ic, but allow this to be overridden at the command line.  For example:
# do wally-pipelined.do ../config/rv32ic
switch $argc {
    0 {vlog +incdir+../config/fpga +incdir+../config/shared ../testbench/testbench-fpga.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv ../src/wally/wallypipelinedsocwrapper.v ../../fpga/sim/*.sv -suppress 2583}
    1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
}
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
vopt -fsmdebug  +acc -gDEBUG=1 work.testbench -o workopt 
vsim workopt -fsmdebug

#profile on

do fpga-wave.do
add log -r /*
#add wave /testbench/ram/RAM[268435456]
#add wave /testbench/ram/RAM[268435457]
#add wave /testbench/ram/RAM[268435458]
#add wave /testbench/ram/RAM[268435459]
#add wave /testbench/ram/RAM[268435460]
#add wave /testbench/ram/RAM[268435461]
#xadd wave /testbench/ram/RAM[268435462]

-- Run the Simulation 
#run 1000
run -all
#quit