2024-10-18 20:18:35 +00:00
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///////////////////////////////////////////
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// lsu.S
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//
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// Written: Kevin Box and Miles Cook kbox@hmc.edu mdcook@hmc.edu 26 March 2023
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//
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// Purpose: Test coverage for lsu
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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2023-04-14 00:50:18 +00:00
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2024-10-18 20:18:35 +00:00
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// load code to initalize stack, handle interrupts, terminate
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2023-04-14 00:50:18 +00:00
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#include "WALLY-init-lib.h"
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main:
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2024-10-18 20:18:35 +00:00
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sfence.vma x0, x0 // sfence.vma to assert TLBFlush
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2023-04-14 00:50:18 +00:00
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2024-01-21 18:03:07 +00:00
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li a0, 0x80000001 # misaligned address
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amoadd.w t0, a0, (a0) # amo access to misaligned address
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2024-10-18 15:42:16 +00:00
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j done
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