cvw/examples/verilog/fulladder/verilate

mirror of https://github.com/openhwgroup/cvw synced 2025-02-02 17:55:19 +00:00
verilator --binary --top-module testbench --trace fulladder.sv
obj_dir/Vtestbench
Verilator fulladder example improvmeents 2024-04-29 05:08:00 +00:00			`verilator --binary --top-module testbench --trace fulladder.sv`
			`obj_dir/Vtestbench`
Progress on Verilator simulation. Full adder compiles and runs. Wally builds. 2023-12-31 17:53:13 +00:00