Added starter code for goboard

This commit is contained in:
Xavi 2023-01-28 13:05:42 -08:00
commit cbfe6bdecc
3 changed files with 205 additions and 0 deletions

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README.md Normal file
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## Required Pkgs
1. iverilog
2. make
3. gtkwave
4. yosys
4. nextpnr
5. icestrom
## Installation
Script assumes Makefile template, and GoBoard constraints file are in the same directory. If this is not wanted
`cat "$DIR"/goboard_Makefile_template >> "$project_name"/Makefile`
and
`cat "$DIR"/Go_Board_Constraints.pcf >> "$project_name"/"$project_name"_constraints_top.pcf`
can be changed to the location of the Makefile template and constraints file
## Usage
Once the script is called, there will be a prompt for the project name - which is the only required field, your name, and sid.
After this the directory structure will be created with source, results, submodules, testbench, and turnin.
## Directories
#### testbench
The testbench directory is where the Makefile will look for the top module which must end in `_tb.v.`
Multiple files may be in this directory, however the desired testbench must be the only file ending with `_tb.v`
#### source
The source directory is for all modules not including the testbench.
#### results
The results directory will contain the output file that can be run with `vvp` as well as the `.vcd` file that can be viewed with `gtkwave`
#### submodules
Other verilog projects which were created using the script can be placed in this directory. `make` will compile `.v` files within the `source` directories of each of the submodules.
#### turnin
All files added to the turnin directory will be compressed when `make tin` is run,
## make commands
#### make
Running `make` while in the project directory will compile the source files and place the output file the `results` directory. Additionaly, this will set the dumpfile to `simx.vcd` in the `results` directory which can be viewed with `gtkwave`.
#### make sim
Running `make sim` while in the project directory will use `vvp` to run the compiled output file.
#### make view
Running `make view` while in the project directory will open the dump file with `gtkwave`.
#### make test
Running `make view` while in the project directory is similar to `make`, however the dumpfile will be set to `/dev/null` to avoid creating a `.vcd` file.
#### make synth
Running `make synth` while in the project directory will use yosys to attempt to synthesize the Verilog for the ice40 FPGA on the GoBoard
#### make par
Running `make par` while in the project directory will use nextpnr-ice40 to place and route on the ice40 FPGA
#### make pack
Running `make par` while in the project directory will use icepack to create a bin file
#### make prog
Running `make par` while in the project directory will program the Goboard with the bin file

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goboard_Makefile_template Normal file
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PATHS := source/
PATHR := results/
PATHB := submodules/
PATHT := turnin/
PATHH := testbench/
# Simulation
OUTPUT := $(PATHR)output
VC := iverilog
SIM := vvp
S_FLAGS := -o
DF_Macro := DUMP_FILE_NAME
WF_viewer := gtkwave
# Synthesis
SYNTH := yosys
SY_FLAGS := -p
SY_TARGET := synth_ice40
SY_OUT_TYPE := json
SY_OUTPUT := $(PATHR)TOP.json
# Place and Route
PAR := nextpnr
PAR_TARGET := ice40
PAR_OPTS := --hx1k --package vq100
CON_FLAG := --pcf
PAR_OUT_TYPE := --asc
PAR_OUTPUT := $(PATHR)TOP.asc
# BIN file
PACKER := icepack
PACK_OUTPUT := $(PATHR)TOP.bin
# Program
PROGRAMMER := iceprog
# Files
NF :=/dev/null
DF := $(PATHR)simx.vcd
README := README.md
# Commands
GET := cp
CLEAN := rm
COMPRESS := tar
C_FLAGS := -czvf
CF := project.tar.gz
CONSTRAINT := $(wildcard ./*_top.pcf)
SOURCES := $(shell find ./ -path '*/$(PATHS)*' -type f)
TESTBENCH := $(wildcard $(PATHH)*_tb.v)
.PHONY: list clean
# Simulation
compile: $(SOURCES) $(TESTBENCH)
$(VC) $(S_FLAGS) $(OUTPUT) -D '$(DF_Macro)="$(DF)"' $(TESTBENCH) $(SOURCES)
sim: $(OUTPUT)
$(SIM) $(OUTPUT)
view: $(DF)
$(WF_viewer) $(DF) &
test: $(SOURCES) $(TESTBENCH)
$(VC) $(S_FLAGS) $(OUTPUT) -D '$(DF_Macro)="$(NF)"' $(TESTBENCH) $(SOURCES)
# Synth
synth: $(SOURCES)
$(SYNTH) $(SY_FLAGS) "$(SY_TARGET) -$(SY_OUT_TYPE) $(SY_OUTPUT)" $(SOURCES)
# Place and Route
par: synth
$(PAR)-$(PAR_TARGET) $(PAR_OPTS) $(CON_FLAG) $(CONSTRAINT) $(PAR_OUT_TYPE) $(PAR_OUTPUT) --$(SY_OUT_TYPE) $(SY_OUTPUT)
# Pack
pack: par
$(PACKER) $(PAR_OUTPUT) $(PACK_OUTPUT)
# Program
prog: pack
$(PROGRAMMER) $(PACK_OUTPUT)
# Compress
tin:
$(GET) $(SOURCES) $(README) $(PATHT)
$(COMPRESS) $(C_FLAGS) $(CF) $(PATHT)
$(OUTPUT): $(SOURCES) $(TESTBENCH)
$(VC) $(S_FLAGS) $(OUTPUT) -D '$(DF_Macro)="$(DF)"' $(TESTBENCH) $(SOURCES)
$(DF): $(OUTPUT)
$(SIM) $(OUTPUT)
clean:
$(CLEAN) $(PATHR)*
list:
$(info $(SOURCES))

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#!/bin/sh
DIR=$(CDPATH= cd -- "$(dirname -- "$0")" && pwd -P)
printf '\nProject name: '; IFS= read -r project_name
printf 'Your name: '; IFS= read -r person_name
printf 'Your SID: '; IFS= read -r person_sid
if [ -z "$project_name" ]
then
printf '\nProject Name Needed!\n';
sleep 1
exit
fi
mkdir -p "$project_name"/source
mkdir -p "$project_name"/results
mkdir -p "$project_name"/submodules
mkdir -p "$project_name"/turnin
mkdir -p "$project_name"/testbench
project_name_tb="$project_name"_tb
cat > "$project_name"/testbench/"$project_name"_tb.v << EOF
\`timescale 1ns/1ps
module $project_name_tb;
initial begin
\$dumpfile(\`DUMP_FILE_NAME);
\$dumpvars(0, $project_name_tb);
end
endmodule
EOF
printf 'Name: %s\nSid: %s\n' "$person_name" "$person_sid" > "$project_name"/README.md
cat "$DIR"/goboard_Makefile_template >> "$project_name"/Makefile
cat "$DIR"/Go_Board_Constraints.pcf >> "$project_name"/"$project_name"_constraints_top.pcf