104 lines
1.9 KiB
Plaintext
104 lines
1.9 KiB
Plaintext
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PATHS := source/
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PATHR := results/
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PATHB := submodules/
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PATHT := turnin/
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PATHH := testbench/
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# Simulation
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OUTPUT := $(PATHR)output
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VC := iverilog
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SIM := vvp
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S_FLAGS := -o
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DF_Macro := DUMP_FILE_NAME
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WF_viewer := gtkwave
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# Synthesis
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SYNTH := yosys
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SY_FLAGS := -p
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SY_TARGET := synth_ice40
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SY_OUT_TYPE := json
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SY_OUTPUT := $(PATHR)TOP.json
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# Place and Route
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PAR := nextpnr
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PAR_TARGET := ice40
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PAR_OPTS := --hx1k --package vq100
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CON_FLAG := --pcf
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PAR_OUT_TYPE := --asc
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PAR_OUTPUT := $(PATHR)TOP.asc
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# BIN file
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PACKER := icepack
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PACK_OUTPUT := $(PATHR)TOP.bin
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# Program
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PROGRAMMER := iceprog
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# Files
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NF :=/dev/null
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DF := $(PATHR)simx.vcd
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README := README.md
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# Commands
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GET := cp
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CLEAN := rm
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COMPRESS := tar
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C_FLAGS := -czvf
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CF := project.tar.gz
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CONSTRAINT := $(wildcard ./*_top.pcf)
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SOURCES := $(shell find ./ -path '*/$(PATHS)*' -type f)
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TESTBENCH := $(wildcard $(PATHH)*_tb.v)
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.PHONY: list clean
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# Simulation
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compile: $(SOURCES) $(TESTBENCH)
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$(VC) $(S_FLAGS) $(OUTPUT) -D '$(DF_Macro)="$(DF)"' $(TESTBENCH) $(SOURCES)
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sim: $(OUTPUT)
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$(SIM) $(OUTPUT)
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view: $(DF)
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$(WF_viewer) $(DF) &
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test: $(SOURCES) $(TESTBENCH)
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$(VC) $(S_FLAGS) $(OUTPUT) -D '$(DF_Macro)="$(NF)"' $(TESTBENCH) $(SOURCES)
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# Synth
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synth: $(SOURCES)
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$(SYNTH) $(SY_FLAGS) "$(SY_TARGET) -$(SY_OUT_TYPE) $(SY_OUTPUT)" $(SOURCES)
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# Place and Route
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par: synth
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$(PAR)-$(PAR_TARGET) $(PAR_OPTS) $(CON_FLAG) $(CONSTRAINT) $(PAR_OUT_TYPE) $(PAR_OUTPUT) --$(SY_OUT_TYPE) $(SY_OUTPUT)
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# Pack
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pack: par
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$(PACKER) $(PAR_OUTPUT) $(PACK_OUTPUT)
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# Program
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prog: pack
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$(PROGRAMMER) $(PACK_OUTPUT)
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# Compress
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tin:
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$(GET) $(SOURCES) $(README) $(PATHT)
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$(COMPRESS) $(C_FLAGS) $(CF) $(PATHT)
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$(OUTPUT): $(SOURCES) $(TESTBENCH)
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$(VC) $(S_FLAGS) $(OUTPUT) -D '$(DF_Macro)="$(DF)"' $(TESTBENCH) $(SOURCES)
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$(DF): $(OUTPUT)
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$(SIM) $(OUTPUT)
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clean:
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$(CLEAN) $(PATHR)*
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list:
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$(info $(SOURCES))
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