forked from Github_Repos/cvw
571 lines
19 KiB
Systemverilog
571 lines
19 KiB
Systemverilog
// riscvpipelined.sv
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// RISC-V pipelined processor
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// From Section 7.6 of Digital Design & Computer Architecture: RISC-V Edition
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// 27 April 2020
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// David_Harris@hmc.edu
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// Sarah.Harris@unlv.edu
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// run 210
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// Expect simulator to print "Simulation succeeded"
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// when the value 25 (0x19) is written to address 100 (0x64)
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// Pipelined implementation of RISC-V (RV32I)
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// User-level Instruction Set Architecture V2.2 (May 7, 2017)
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// Implements a subset of the base integer instructions:
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// lw, sw
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// add, sub, and, or, slt,
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// addi, andi, ori, slti
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// beq
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// jal
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// Exceptions, traps, and interrupts not implemented
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// little-endian memory
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// 31 32-bit registers x1-x31, x0 hardwired to 0
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// R-Type instructions
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// add, sub, and, or, slt
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// INSTR rd, rs1, rs2
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// Instr[31:25] = funct7 (funct7b5 & opb5 = 1 for sub, 0 for others)
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// Instr[24:20] = rs2
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// Instr[19:15] = rs1
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// Instr[14:12] = funct3
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// Instr[11:7] = rd
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// Instr[6:0] = opcode
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// I-Type Instructions
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// lw, I-type ALU (addi, andi, ori, slti)
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// lw: INSTR rd, imm(rs1)
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// I-type ALU: INSTR rd, rs1, imm (12-bit signed)
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// Instr[31:20] = imm[11:0]
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// Instr[24:20] = rs2
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// Instr[19:15] = rs1
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// Instr[14:12] = funct3
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// Instr[11:7] = rd
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// Instr[6:0] = opcode
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// S-Type Instruction
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// sw rs2, imm(rs1) (store rs2 into address specified by rs1 + immm)
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// Instr[31:25] = imm[11:5] (offset[11:5])
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// Instr[24:20] = rs2 (src)
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// Instr[19:15] = rs1 (base)
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// Instr[14:12] = funct3
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// Instr[11:7] = imm[4:0] (offset[4:0])
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// Instr[6:0] = opcode
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// B-Type Instruction
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// beq rs1, rs2, imm (PCTarget = PC + (signed imm x 2))
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// Instr[31:25] = imm[12], imm[10:5]
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// Instr[24:20] = rs2
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// Instr[19:15] = rs1
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// Instr[14:12] = funct3
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// Instr[11:7] = imm[4:1], imm[11]
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// Instr[6:0] = opcode
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// J-Type Instruction
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// jal rd, imm (signed imm is multiplied by 2 and added to PC, rd = PC+4)
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// Instr[31:12] = imm[20], imm[10:1], imm[11], imm[19:12]
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// Instr[11:7] = rd
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// Instr[6:0] = opcode
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// Instruction opcode funct3 funct7
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// add 0110011 000 0000000
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// sub 0110011 000 0100000
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// and 0110011 111 0000000
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// or 0110011 110 0000000
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// slt 0110011 010 0000000
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// addi 0010011 000 immediate
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// andi 0010011 111 immediate
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// ori 0010011 110 immediate
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// slti 0010011 010 immediate
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// beq 1100011 000 immediate
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// lw 0000011 010 immediate
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// sw 0100011 010 immediate
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// jal 1101111 immediate immediate
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module testbench();
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logic clk;
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logic reset;
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logic [31:0] WriteData, DataAdr;
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logic MemWrite;
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// instantiate device to be tested
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top dut(clk, reset, WriteData, DataAdr, MemWrite);
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// initialize test
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initial
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begin
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reset <= 1; # 22; reset <= 0;
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end
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// generate clock to sequence tests
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always
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begin
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clk <= 1; # 5; clk <= 0; # 5;
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end
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// check results
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always @(negedge clk)
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begin
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if(MemWrite) begin
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if(DataAdr === 100 & WriteData === 25) begin
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$display("Simulation succeeded");
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$stop;
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end else if (DataAdr !== 96) begin
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$display("Simulation failed");
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$stop;
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end
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end
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end
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endmodule
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module top(input logic clk, reset,
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output logic [31:0] WriteDataM, DataAdrM,
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output logic MemWriteM);
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logic [31:0] PCF, InstrF, ReadDataM;
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// instantiate processor and memories
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riscv riscv(clk, reset, PCF, InstrF, MemWriteM, DataAdrM,
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WriteDataM, ReadDataM);
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imem imem(PCF, InstrF);
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dmem dmem(clk, MemWriteM, DataAdrM, WriteDataM, ReadDataM);
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endmodule
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module riscv(input logic clk, reset,
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output logic [31:0] PCF,
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input logic [31:0] InstrF,
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output logic MemWriteM,
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output logic [31:0] ALUResultM, WriteDataM,
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input logic [31:0] ReadDataM);
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logic [6:0] opD;
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logic [2:0] funct3D;
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logic funct7b5D;
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logic [1:0] ImmSrcD;
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logic ZeroE;
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logic PCSrcE;
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logic [2:0] ALUControlE;
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logic ALUSrcE;
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logic ResultSrcEb0;
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logic RegWriteM;
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logic [1:0] ResultSrcW;
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logic RegWriteW;
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logic [1:0] ForwardAE, ForwardBE;
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logic StallF, StallD, FlushD, FlushE;
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logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW;
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controller c(clk, reset,
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opD, funct3D, funct7b5D, ImmSrcD,
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FlushE, ZeroE, PCSrcE, ALUControlE, ALUSrcE, ResultSrcEb0,
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MemWriteM, RegWriteM,
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RegWriteW, ResultSrcW);
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datapath dp(clk, reset,
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StallF, PCF, InstrF,
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opD, funct3D, funct7b5D, StallD, FlushD, ImmSrcD,
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FlushE, ForwardAE, ForwardBE, PCSrcE, ALUControlE, ALUSrcE, ZeroE,
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MemWriteM, WriteDataM, ALUResultM, ReadDataM,
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RegWriteW, ResultSrcW,
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Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW);
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hazard hu(Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW,
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PCSrcE, ResultSrcEb0, RegWriteM, RegWriteW,
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ForwardAE, ForwardBE, StallF, StallD, FlushD, FlushE);
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endmodule
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module controller(input logic clk, reset,
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// Decode stage control signals
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input logic [6:0] opD,
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input logic [2:0] funct3D,
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input logic funct7b5D,
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output logic [1:0] ImmSrcD,
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// Execute stage control signals
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input logic FlushE,
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input logic ZeroE,
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output logic PCSrcE, // for datapath and Hazard Unit
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output logic [2:0] ALUControlE,
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output logic ALUSrcE,
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output logic ResultSrcEb0, // for Hazard Unit
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// Memory stage control signals
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output logic MemWriteM,
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output logic RegWriteM, // for Hazard Unit
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// Writeback stage control signals
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output logic RegWriteW, // for datapath and Hazard Unit
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output logic [1:0] ResultSrcW);
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// pipelined control signals
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logic RegWriteD, RegWriteE;
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logic [1:0] ResultSrcD, ResultSrcE, ResultSrcM;
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logic MemWriteD, MemWriteE;
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logic JumpD, JumpE;
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logic BranchD, BranchE;
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logic [1:0] ALUOpD;
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logic [2:0] ALUControlD;
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logic ALUSrcD;
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// Decode stage logic
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maindec md(opD, ResultSrcD, MemWriteD, BranchD,
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ALUSrcD, RegWriteD, JumpD, ImmSrcD, ALUOpD);
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aludec ad(opD[5], funct3D, funct7b5D, ALUOpD, ALUControlD);
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// Execute stage pipeline control register and logic
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floprc #(10) controlregE(clk, reset, FlushE,
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{RegWriteD, ResultSrcD, MemWriteD, JumpD, BranchD, ALUControlD, ALUSrcD},
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{RegWriteE, ResultSrcE, MemWriteE, JumpE, BranchE, ALUControlE, ALUSrcE});
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assign PCSrcE = (BranchE & ZeroE) | JumpE;
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assign ResultSrcEb0 = ResultSrcE[0];
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// Memory stage pipeline control register
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flopr #(4) controlregM(clk, reset,
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{RegWriteE, ResultSrcE, MemWriteE},
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{RegWriteM, ResultSrcM, MemWriteM});
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// Writeback stage pipeline control register
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flopr #(3) controlregW(clk, reset,
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{RegWriteM, ResultSrcM},
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{RegWriteW, ResultSrcW});
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endmodule
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module maindec(input logic [6:0] op,
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output logic [1:0] ResultSrc,
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output logic MemWrite,
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output logic Branch, ALUSrc,
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output logic RegWrite, Jump,
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output logic [1:0] ImmSrc,
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output logic [1:0] ALUOp);
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logic [10:0] controls;
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assign {RegWrite, ImmSrc, ALUSrc, MemWrite,
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ResultSrc, Branch, ALUOp, Jump} = controls;
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always_comb
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case(op)
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// RegWrite_ImmSrc_ALUSrc_MemWrite_ResultSrc_Branch_ALUOp_Jump
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7'b0000011: controls = 11'b1_00_1_0_01_0_00_0; // lw
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7'b0100011: controls = 11'b0_01_1_1_00_0_00_0; // sw
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7'b0110011: controls = 11'b1_xx_0_0_00_0_10_0; // R-type
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7'b1100011: controls = 11'b0_10_0_0_00_1_01_0; // beq
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7'b0010011: controls = 11'b1_00_1_0_00_0_10_0; // I-type ALU
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7'b1101111: controls = 11'b1_11_0_0_10_0_00_1; // jal
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7'b0000000: controls = 11'b0_00_0_0_00_0_00_0; // need valid values at reset
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default: controls = 11'bx_xx_x_x_xx_x_xx_x; // non-implemented instruction
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endcase
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endmodule
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module aludec(input logic opb5,
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input logic [2:0] funct3,
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input logic funct7b5,
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input logic [1:0] ALUOp,
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output logic [2:0] ALUControl);
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logic RtypeSub;
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assign RtypeSub = funct7b5 & opb5; // TRUE for R-type subtract instruction
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always_comb
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case(ALUOp)
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2'b00: ALUControl = 3'b000; // addition
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2'b01: ALUControl = 3'b001; // subtraction
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default: case(funct3) // R-type or I-type ALU
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3'b000: if (RtypeSub)
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ALUControl = 3'b001; // sub
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else
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ALUControl = 3'b000; // add, addi
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3'b010: ALUControl = 3'b101; // slt, slti
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3'b110: ALUControl = 3'b011; // or, ori
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3'b111: ALUControl = 3'b010; // and, andi
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default: ALUControl = 3'bxxx; // ???
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endcase
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endcase
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endmodule
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module datapath(input logic clk, reset,
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// Fetch stage signals
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input logic StallF,
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output logic [31:0] PCF,
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input logic [31:0] InstrF,
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// Decode stage signals
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output logic [6:0] opD,
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output logic [2:0] funct3D,
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output logic funct7b5D,
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input logic StallD, FlushD,
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input logic [1:0] ImmSrcD,
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// Execute stage signals
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input logic FlushE,
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input logic [1:0] ForwardAE, ForwardBE,
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input logic PCSrcE,
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input logic [2:0] ALUControlE,
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input logic ALUSrcE,
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output logic ZeroE,
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// Memory stage signals
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input logic MemWriteM,
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output logic [31:0] WriteDataM, ALUResultM,
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input logic [31:0] ReadDataM,
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// Writeback stage signals
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input logic RegWriteW,
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input logic [1:0] ResultSrcW,
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// Hazard Unit signals
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output logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E,
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output logic [4:0] RdE, RdM, RdW);
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// Fetch stage signals
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logic [31:0] PCNextF, PCPlus4F;
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// Decode stage signals
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logic [31:0] InstrD;
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logic [31:0] PCD, PCPlus4D;
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logic [31:0] RD1D, RD2D;
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logic [31:0] ImmExtD;
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logic [4:0] RdD;
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// Execute stage signals
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logic [31:0] RD1E, RD2E;
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logic [31:0] PCE, ImmExtE;
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logic [31:0] SrcAE, SrcBE;
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logic [31:0] ALUResultE;
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logic [31:0] WriteDataE;
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logic [31:0] PCPlus4E;
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logic [31:0] PCTargetE;
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// Memory stage signals
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logic [31:0] PCPlus4M;
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// Writeback stage signals
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logic [31:0] ALUResultW;
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logic [31:0] ReadDataW;
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logic [31:0] PCPlus4W;
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logic [31:0] ResultW;
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// Fetch stage pipeline register and logic
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mux2 #(32) pcmux(PCPlus4F, PCTargetE, PCSrcE, PCNextF);
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flopenr #(32) pcreg(clk, reset, ~StallF, PCNextF, PCF);
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adder pcadd(PCF, 32'h4, PCPlus4F);
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// Decode stage pipeline register and logic
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flopenrc #(96) regD(clk, reset, FlushD, ~StallD,
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{InstrF, PCF, PCPlus4F},
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{InstrD, PCD, PCPlus4D});
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assign opD = InstrD[6:0];
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assign funct3D = InstrD[14:12];
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assign funct7b5D = InstrD[30];
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assign Rs1D = InstrD[19:15];
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assign Rs2D = InstrD[24:20];
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assign RdD = InstrD[11:7];
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regfile rf(clk, RegWriteW, Rs1D, Rs2D, RdW, ResultW, RD1D, RD2D);
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extend ext(InstrD[31:7], ImmSrcD, ImmExtD);
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// Execute stage pipeline register and logic
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floprc #(175) regE(clk, reset, FlushE,
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{RD1D, RD2D, PCD, Rs1D, Rs2D, RdD, ImmExtD, PCPlus4D},
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{RD1E, RD2E, PCE, Rs1E, Rs2E, RdE, ImmExtE, PCPlus4E});
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mux3 #(32) faemux(RD1E, ResultW, ALUResultM, ForwardAE, SrcAE);
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mux3 #(32) fbemux(RD2E, ResultW, ALUResultM, ForwardBE, WriteDataE);
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mux2 #(32) srcbmux(WriteDataE, ImmExtE, ALUSrcE, SrcBE);
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alu alu(SrcAE, SrcBE, ALUControlE, ALUResultE, ZeroE);
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adder branchadd(ImmExtE, PCE, PCTargetE);
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// Memory stage pipeline register
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flopr #(101) regM(clk, reset,
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{ALUResultE, WriteDataE, RdE, PCPlus4E},
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{ALUResultM, WriteDataM, RdM, PCPlus4M});
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// Writeback stage pipeline register and logic
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flopr #(101) regW(clk, reset,
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{ALUResultM, ReadDataM, RdM, PCPlus4M},
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{ALUResultW, ReadDataW, RdW, PCPlus4W});
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mux3 #(32) resultmux(ALUResultW, ReadDataW, PCPlus4W, ResultSrcW, ResultW);
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endmodule
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// Hazard Unit: forward, stall, and flush
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module hazard(input logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW,
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input logic PCSrcE, ResultSrcEb0,
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input logic RegWriteM, RegWriteW,
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output logic [1:0] ForwardAE, ForwardBE,
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output logic StallF, StallD, FlushD, FlushE);
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logic lwStallD;
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// forwarding logic
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always_comb begin
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ForwardAE = 2'b00;
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ForwardBE = 2'b00;
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if (Rs1E != 5'b0)
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if ((Rs1E == RdM) & RegWriteM) ForwardAE = 2'b10;
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else if ((Rs1E == RdW) & RegWriteW) ForwardAE = 2'b01;
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if (Rs2E != 5'b0)
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if ((Rs2E == RdM) & RegWriteM) ForwardBE = 2'b10;
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else if ((Rs2E == RdW) & RegWriteW) ForwardBE = 2'b01;
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end
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// stalls and flushes
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assign lwStallD = ResultSrcEb0 & ((Rs1D == RdE) | (Rs2D == RdE));
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assign StallD = lwStallD;
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assign StallF = lwStallD;
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assign FlushD = PCSrcE;
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assign FlushE = lwStallD | PCSrcE;
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endmodule
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module regfile(input logic clk,
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input logic we3,
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input logic [ 4:0] a1, a2, a3,
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input logic [31:0] wd3,
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output logic [31:0] rd1, rd2);
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logic [31:0] rf[31:0];
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// three ported register file
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// read two ports combinationally (A1/RD1, A2/RD2)
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// write third port on rising edge of clock (A3/WD3/WE3)
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// write occurs on falling edge of clock
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// register 0 hardwired to 0
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always_ff @(negedge clk)
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if (we3) rf[a3] <= wd3;
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assign rd1 = (a1 != 0) ? rf[a1] : 0;
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assign rd2 = (a2 != 0) ? rf[a2] : 0;
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endmodule
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module adder(input [31:0] a, b,
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output [31:0] y);
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assign y = a + b;
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endmodule
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module extend(input logic [31:7] instr,
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input logic [1:0] immsrc,
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output logic [31:0] immext);
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always_comb
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case(immsrc)
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// I-type
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2'b00: immext = {{20{instr[31]}}, instr[31:20]};
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// S-type (stores)
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2'b01: immext = {{20{instr[31]}}, instr[31:25], instr[11:7]};
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// B-type (branches)
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2'b10: immext = {{20{instr[31]}}, instr[7], instr[30:25], instr[11:8], 1'b0};
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// J-type (jal)
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2'b11: immext = {{12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0};
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default: immext = 32'bx; // undefined
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endcase
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endmodule
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module flopr #(parameter WIDTH = 8)
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(input logic clk, reset,
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input logic [WIDTH-1:0] d,
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output logic [WIDTH-1:0] q);
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|
|
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always_ff @(posedge clk, posedge reset)
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if (reset) q <= 0;
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else q <= d;
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endmodule
|
|
|
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module flopenr #(parameter WIDTH = 8)
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(input logic clk, reset, en,
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input logic [WIDTH-1:0] d,
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|
output logic [WIDTH-1:0] q);
|
|
|
|
always_ff @(posedge clk, posedge reset)
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|
if (reset) q <= 0;
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else if (en) q <= d;
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|
endmodule
|
|
|
|
module flopenrc #(parameter WIDTH = 8)
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|
(input logic clk, reset, clear, en,
|
|
input logic [WIDTH-1:0] d,
|
|
output logic [WIDTH-1:0] q);
|
|
|
|
always_ff @(posedge clk, posedge reset)
|
|
if (reset) q <= 0;
|
|
else if (en)
|
|
if (clear) q <= 0;
|
|
else q <= d;
|
|
endmodule
|
|
|
|
module floprc #(parameter WIDTH = 8)
|
|
(input logic clk,
|
|
input logic reset,
|
|
input logic clear,
|
|
input logic [WIDTH-1:0] d,
|
|
output logic [WIDTH-1:0] q);
|
|
|
|
always_ff @(posedge clk, posedge reset)
|
|
if (reset) q <= 0;
|
|
else
|
|
if (clear) q <= 0;
|
|
else q <= d;
|
|
endmodule
|
|
|
|
module mux2 #(parameter WIDTH = 8)
|
|
(input logic [WIDTH-1:0] d0, d1,
|
|
input logic s,
|
|
output logic [WIDTH-1:0] y);
|
|
|
|
assign y = s ? d1 : d0;
|
|
endmodule
|
|
|
|
module mux3 #(parameter WIDTH = 8)
|
|
(input logic [WIDTH-1:0] d0, d1, d2,
|
|
input logic [1:0] s,
|
|
output logic [WIDTH-1:0] y);
|
|
|
|
assign y = s[1] ? d2 : (s[0] ? d1 : d0);
|
|
endmodule
|
|
|
|
module imem(input logic [31:0] a,
|
|
output logic [31:0] rd);
|
|
|
|
logic [31:0] RAM[63:0];
|
|
|
|
initial
|
|
$readmemh("riscvtest.txt",RAM);
|
|
|
|
assign rd = RAM[a[31:2]]; // word aligned
|
|
endmodule
|
|
|
|
module dmem(input logic clk, we,
|
|
input logic [31:0] a, wd,
|
|
output logic [31:0] rd);
|
|
|
|
logic [31:0] RAM[63:0];
|
|
|
|
assign rd = RAM[a[31:2]]; // word aligned
|
|
|
|
always_ff @(posedge clk)
|
|
if (we) RAM[a[31:2]] <= wd;
|
|
endmodule
|
|
|
|
module alu(input logic [31:0] a, b,
|
|
input logic [2:0] alucontrol,
|
|
output logic [31:0] result,
|
|
output logic zero);
|
|
|
|
logic [31:0] condinvb, sum;
|
|
logic v; // overflow
|
|
logic isAddSub; // true when is add or subtract operation
|
|
|
|
assign condinvb = alucontrol[0] ? ~b : b;
|
|
assign sum = a + condinvb + alucontrol[0];
|
|
assign isAddSub = ~alucontrol[2] & ~alucontrol[1] |
|
|
~alucontrol[1] & alucontrol[0];
|
|
|
|
always_comb
|
|
case (alucontrol)
|
|
3'b000: result = sum; // add
|
|
3'b001: result = sum; // subtract
|
|
3'b010: result = a & b; // and
|
|
3'b011: result = a | b; // or
|
|
3'b100: result = a ^ b; // xor
|
|
3'b101: result = sum[31] ^ v; // slt
|
|
3'b110: result = a << b[4:0]; // sll
|
|
3'b111: result = a >> b[4:0]; // srl
|
|
default: result = 32'bx;
|
|
endcase
|
|
|
|
assign zero = (result == 32'b0);
|
|
assign v = ~(alucontrol[0] ^ a[31] ^ b[31]) & (a[31] ^ sum[31]) & isAddSub;
|
|
|
|
endmodule
|
|
|