forked from Github_Repos/cvw
103 lines
4.0 KiB
Systemverilog
103 lines
4.0 KiB
Systemverilog
/*
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* Copyright (c) 2005-2023 Imperas Software Ltd., www.imperas.com
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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* either express or implied.
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*
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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*/
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`define NUM_REGS 32
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`define NUM_CSRS 4096
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interface rvviTrace
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#(
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parameter int ILEN = 32, // Instruction length in bits
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parameter int XLEN = 32, // GPR length in bits
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parameter int FLEN = 32, // FPR length in bits
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parameter int VLEN = 256, // Vector register size in bits
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parameter int NHART = 1, // Number of harts reported
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parameter int RETIRE = 1 // Number of instructions that can retire during valid event
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);
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//
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// RISCV output signals
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//
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wire clk; // Interface clock
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wire valid [(NHART-1):0][(RETIRE-1):0]; // Retired instruction
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wire [63:0] order [(NHART-1):0][(RETIRE-1):0]; // Unique instruction order count (no gaps or reuse)
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wire [(ILEN-1):0] insn [(NHART-1):0][(RETIRE-1):0]; // Instruction bit pattern
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wire trap [(NHART-1):0][(RETIRE-1):0]; // Trapped instruction (External to Core, eg Memory Subsystem)
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wire halt [(NHART-1):0][(RETIRE-1):0]; // Halted instruction
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wire intr [(NHART-1):0][(RETIRE-1):0]; // (RVFI Legacy) Flag first instruction of trap handler
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wire [1:0] mode [(NHART-1):0][(RETIRE-1):0]; // Privilege mode of operation
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wire [1:0] ixl [(NHART-1):0][(RETIRE-1):0]; // XLEN mode 32/64 bit
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wire [(XLEN-1):0] pc_rdata [(NHART-1):0][(RETIRE-1):0]; // PC of insn
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wire [(XLEN-1):0] pc_wdata [(NHART-1):0][(RETIRE-1):0]; // PC of next instruction
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// X Registers
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wire [31:0][(XLEN-1):0] x_wdata [(NHART-1):0][(RETIRE-1):0]; // X data value
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wire [31:0] x_wb [(NHART-1):0][(RETIRE-1):0]; // X data writeback (change) flag
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// F Registers
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wire [31:0][(FLEN-1):0] f_wdata [(NHART-1):0][(RETIRE-1):0]; // F data value
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wire [31:0] f_wb [(NHART-1):0][(RETIRE-1):0]; // F data writeback (change) flag
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// V Registers
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wire [31:0][(VLEN-1):0] v_wdata [(NHART-1):0][(RETIRE-1):0]; // V data value
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wire [31:0] v_wb [(NHART-1):0][(RETIRE-1):0]; // V data writeback (change) flag
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// Control & State Registers
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wire [4095:0][(XLEN-1):0] csr [(NHART-1):0][(RETIRE-1):0]; // Full CSR Address range
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wire [4095:0] csr_wb [(NHART-1):0][(RETIRE-1):0]; // CSR writeback (change) flag
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wire lrsc_cancel[(NHART-1):0][(RETIRE-1):0]; // Implementation defined cancel
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//
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// Synchronization of NETs
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//
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wire clkD;
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assign #1 clkD = clk;
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longint vslot;
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always @(posedge clk) vslot++;
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string name[$];
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int value[$];
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longint tslot[$];
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int nets[string];
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function automatic void net_push(input string vname, input int vvalue);
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name.push_front(vname);
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value.push_front(vvalue);
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tslot.push_front(vslot);
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endfunction
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function automatic int net_pop(output string vname, output int vvalue, output longint vslot);
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int ok;
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string msg;
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if (name.size() > 0) begin
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vname = name.pop_back();
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vvalue = value.pop_back();
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vslot = tslot.pop_back();
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nets[vname] = vvalue;
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ok = 1;
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end else begin
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ok = 0;
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end
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return ok;
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endfunction
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endinterface
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