// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version   : 0.5.1
// timestamp : Mon Aug  2 08:58:53 2021 GMT
// usage     : riscv_ctg \
//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
//                  --base-isa rv32e \
//                  --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the srli instruction of the RISC-V E extension for the srli covergroup.
// 
#define RVTEST_E
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32E")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",srli)

RVTEST_SIGBASE( x1,signature_x1_1)

inst_0:
// rs1 != rd, rs1==x4, rd==x5, rs1_val < 0 and imm_val == (xlen-1), rs1_val == -65, rs1_val < 0 and imm_val > 0 and imm_val < xlen
// opcode: srli ; op1:x4; dest:x5; op1val:-0x41;  immval:0x1f
TEST_IMM_OP( srli, x5, x4, 0x1, -0x41, 0x1f, x1, 0, x10)

inst_1:
// rs1 == rd, rs1==x9, rd==x9, rs1_val == 2147483647, rs1_val == (2**(xlen-1)-1) and imm_val >= 0 and imm_val < xlen, rs1_val > 0 and imm_val > 0 and imm_val < xlen, imm_val == 8
// opcode: srli ; op1:x9; dest:x9; op1val:0x7fffffff;  immval:0x8
TEST_IMM_OP( srli, x9, x9, 0x7fffff, 0x7fffffff, 0x8, x1, 4, x10)

inst_2:
// rs1==x0, rd==x6, rs1_val == -1073741825, imm_val == 23
// opcode: srli ; op1:x0; dest:x6; op1val:0x0;  immval:0x17
TEST_IMM_OP( srli, x6, x0, 0x0, 0x0, 0x17, x1, 8, x10)

inst_3:
// rs1==x12, rd==x4, rs1_val == -536870913, 
// opcode: srli ; op1:x12; dest:x4; op1val:-0x20000001;  immval:0x6
TEST_IMM_OP( srli, x4, x12, 0x37fffff, -0x20000001, 0x6, x1, 12, x10)

inst_4:
// rs1==x8, rd==x14, rs1_val == -268435457, imm_val == 10
// opcode: srli ; op1:x8; dest:x14; op1val:-0x10000001;  immval:0xa
TEST_IMM_OP( srli, x14, x8, 0x3bffff, -0x10000001, 0xa, x1, 16, x10)

inst_5:
// rs1==x7, rd==x3, rs1_val == -134217729, imm_val == 2
// opcode: srli ; op1:x7; dest:x3; op1val:-0x8000001;  immval:0x2
TEST_IMM_OP( srli, x3, x7, 0x3dffffff, -0x8000001, 0x2, x1, 20, x10)

inst_6:
// rs1==x6, rd==x2, rs1_val == -67108865, 
// opcode: srli ; op1:x6; dest:x2; op1val:-0x4000001;  immval:0x12
TEST_IMM_OP( srli, x2, x6, 0x3eff, -0x4000001, 0x12, x1, 24, x10)

inst_7:
// rs1==x11, rd==x15, rs1_val == -33554433, imm_val == 16
// opcode: srli ; op1:x11; dest:x15; op1val:-0x2000001;  immval:0x10
TEST_IMM_OP( srli, x15, x11, 0xfdff, -0x2000001, 0x10, x1, 28, x10)
RVTEST_SIGBASE( x4,signature_x4_0)

inst_8:
// rs1==x5, rd==x13, rs1_val == -16777217, imm_val == 1
// opcode: srli ; op1:x5; dest:x13; op1val:-0x1000001;  immval:0x1
TEST_IMM_OP( srli, x13, x5, 0x7f7fffff, -0x1000001, 0x1, x4, 0, x6)

inst_9:
// rs1==x15, rd==x11, rs1_val == -8388609, 
// opcode: srli ; op1:x15; dest:x11; op1val:-0x800001;  immval:0x11
TEST_IMM_OP( srli, x11, x15, 0x7fbf, -0x800001, 0x11, x4, 4, x6)

inst_10:
// rs1==x2, rd==x12, rs1_val == -4194305, imm_val == 15
// opcode: srli ; op1:x2; dest:x12; op1val:-0x400001;  immval:0xf
TEST_IMM_OP( srli, x12, x2, 0x1ff7f, -0x400001, 0xf, x4, 8, x6)

inst_11:
// rs1==x14, rd==x7, rs1_val == -2097153, 
// opcode: srli ; op1:x14; dest:x7; op1val:-0x200001;  immval:0x7
TEST_IMM_OP( srli, x7, x14, 0x1ffbfff, -0x200001, 0x7, x4, 12, x6)

inst_12:
// rs1==x13, rd==x0, rs1_val == -1048577, 
// opcode: srli ; op1:x13; dest:x0; op1val:-0x100001;  immval:0xc
TEST_IMM_OP( srli, x0, x13, 0, -0x100001, 0xc, x4, 16, x6)

inst_13:
// rs1==x3, rd==x10, rs1_val == -524289, imm_val == 21
// opcode: srli ; op1:x3; dest:x10; op1val:-0x80001;  immval:0x15
TEST_IMM_OP( srli, x10, x3, 0x7ff, -0x80001, 0x15, x4, 20, x6)

inst_14:
// rs1==x10, rd==x1, rs1_val == -262145, 
// opcode: srli ; op1:x10; dest:x1; op1val:-0x40001;  immval:0x10
TEST_IMM_OP( srli, x1, x10, 0xfffb, -0x40001, 0x10, x4, 24, x6)

inst_15:
// rs1==x1, rd==x8, rs1_val == -131073, 
// opcode: srli ; op1:x1; dest:x8; op1val:-0x20001;  immval:0x11
TEST_IMM_OP( srli, x8, x1, 0x7ffe, -0x20001, 0x11, x4, 28, x2)
RVTEST_SIGBASE( x1,signature_x1_2)

inst_16:
// rs1_val == -65537, 
// opcode: srli ; op1:x10; dest:x11; op1val:-0x10001;  immval:0xb
TEST_IMM_OP( srli, x11, x10, 0x1fffdf, -0x10001, 0xb, x1, 0, x2)

inst_17:
// rs1_val == -32769, 
// opcode: srli ; op1:x10; dest:x11; op1val:-0x8001;  immval:0x12
TEST_IMM_OP( srli, x11, x10, 0x3fff, -0x8001, 0x12, x1, 4, x2)

inst_18:
// rs1_val == -16385, rs1_val < 0 and imm_val == 0
// opcode: srli ; op1:x10; dest:x11; op1val:-0x4001;  immval:0x0
TEST_IMM_OP( srli, x11, x10, 0xffffbfff, -0x4001, 0x0, x1, 8, x2)

inst_19:
// rs1_val == -8193, 
// opcode: srli ; op1:x10; dest:x11; op1val:-0x2001;  immval:0x13
TEST_IMM_OP( srli, x11, x10, 0x1fff, -0x2001, 0x13, x1, 12, x2)

inst_20:
// rs1_val == -4097, 
// opcode: srli ; op1:x10; dest:x11; op1val:-0x1001;  immval:0xa
TEST_IMM_OP( srli, x11, x10, 0x3ffffb, -0x1001, 0xa, x1, 16, x2)

inst_21:
// rs1_val == -2049, 
// opcode: srli ; op1:x10; dest:x11; op1val:-0x801;  immval:0x15
TEST_IMM_OP( srli, x11, x10, 0x7ff, -0x801, 0x15, x1, 20, x2)

inst_22:
// rs1_val == -1025, 
// opcode: srli ; op1:x10; dest:x11; op1val:-0x401;  immval:0x6
TEST_IMM_OP( srli, x11, x10, 0x3ffffef, -0x401, 0x6, x1, 24, x2)

inst_23:
// rs1_val == -513, 
// opcode: srli ; op1:x10; dest:x11; op1val:-0x201;  immval:0x13
TEST_IMM_OP( srli, x11, x10, 0x1fff, -0x201, 0x13, x1, 28, x2)

inst_24:
// rs1_val == -257, 
// opcode: srli ; op1:x10; dest:x11; op1val:-0x101;  immval:0x8
TEST_IMM_OP( srli, x11, x10, 0xfffffe, -0x101, 0x8, x1, 32, x2)

inst_25:
// rs1_val == -129, 
// opcode: srli ; op1:x10; dest:x11; op1val:-0x81;  immval:0x8
TEST_IMM_OP( srli, x11, x10, 0xffffff, -0x81, 0x8, x1, 36, x2)

inst_26:
// rs1_val == -33, 
// opcode: srli ; op1:x10; dest:x11; op1val:-0x21;  immval:0x2
TEST_IMM_OP( srli, x11, x10, 0x3ffffff7, -0x21, 0x2, x1, 40, x2)

inst_27:
// rs1_val == -17, 
// opcode: srli ; op1:x10; dest:x11; op1val:-0x11;  immval:0x12
TEST_IMM_OP( srli, x11, x10, 0x3fff, -0x11, 0x12, x1, 44, x2)

inst_28:
// rs1_val == -9, 
// opcode: srli ; op1:x10; dest:x11; op1val:-0x9;  immval:0x2
TEST_IMM_OP( srli, x11, x10, 0x3ffffffd, -0x9, 0x2, x1, 48, x2)

inst_29:
// rs1_val == -5, 
// opcode: srli ; op1:x10; dest:x11; op1val:-0x5;  immval:0x6
TEST_IMM_OP( srli, x11, x10, 0x3ffffff, -0x5, 0x6, x1, 52, x2)

inst_30:
// rs1_val == -3, 
// opcode: srli ; op1:x10; dest:x11; op1val:-0x3;  immval:0xf
TEST_IMM_OP( srli, x11, x10, 0x1ffff, -0x3, 0xf, x1, 56, x2)

inst_31:
// rs1_val == -2, 
// opcode: srli ; op1:x10; dest:x11; op1val:-0x2;  immval:0xc
TEST_IMM_OP( srli, x11, x10, 0xfffff, -0x2, 0xc, x1, 60, x2)

inst_32:
// imm_val == 27, rs1_val == 262144
// opcode: srli ; op1:x10; dest:x11; op1val:0x40000;  immval:0x1b
TEST_IMM_OP( srli, x11, x10, 0x0, 0x40000, 0x1b, x1, 64, x2)

inst_33:
// imm_val == 29, 
// opcode: srli ; op1:x10; dest:x11; op1val:-0x40000000;  immval:0x1d
TEST_IMM_OP( srli, x11, x10, 0x6, -0x40000000, 0x1d, x1, 68, x2)

inst_34:
// imm_val == 30, rs1_val == 64
// opcode: srli ; op1:x10; dest:x11; op1val:0x40;  immval:0x1e
TEST_IMM_OP( srli, x11, x10, 0x0, 0x40, 0x1e, x1, 72, x2)

inst_35:
// rs1_val == -2147483648, rs1_val == (-2**(xlen-1)) and imm_val >= 0 and imm_val < xlen
// opcode: srli ; op1:x10; dest:x11; op1val:-0x80000000;  immval:0xa
TEST_IMM_OP( srli, x11, x10, 0x200000, -0x80000000, 0xa, x1, 76, x2)

inst_36:
// rs1_val == 1073741824, rs1_val > 0 and imm_val == 0
// opcode: srli ; op1:x10; dest:x11; op1val:0x40000000;  immval:0x0
TEST_IMM_OP( srli, x11, x10, 0x40000000, 0x40000000, 0x0, x1, 80, x2)

inst_37:
// rs1_val == 536870912, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x20000000;  immval:0x11
TEST_IMM_OP( srli, x11, x10, 0x1000, 0x20000000, 0x11, x1, 84, x2)

inst_38:
// rs1_val == 268435456, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x10000000;  immval:0x11
TEST_IMM_OP( srli, x11, x10, 0x800, 0x10000000, 0x11, x1, 88, x2)

inst_39:
// rs1_val == 134217728, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x8000000;  immval:0xb
TEST_IMM_OP( srli, x11, x10, 0x10000, 0x8000000, 0xb, x1, 92, x2)

inst_40:
// rs1_val == 67108864, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x4000000;  immval:0x1e
TEST_IMM_OP( srli, x11, x10, 0x0, 0x4000000, 0x1e, x1, 96, x2)

inst_41:
// rs1_val == 33554432, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x2000000;  immval:0x13
TEST_IMM_OP( srli, x11, x10, 0x40, 0x2000000, 0x13, x1, 100, x2)

inst_42:
// rs1_val == 16777216, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x1000000;  immval:0xd
TEST_IMM_OP( srli, x11, x10, 0x800, 0x1000000, 0xd, x1, 104, x2)

inst_43:
// rs1_val == 8388608, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x800000;  immval:0x7
TEST_IMM_OP( srli, x11, x10, 0x10000, 0x800000, 0x7, x1, 108, x2)

inst_44:
// rs1_val == 4194304, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x400000;  immval:0x6
TEST_IMM_OP( srli, x11, x10, 0x10000, 0x400000, 0x6, x1, 112, x2)

inst_45:
// rs1_val == 2097152, imm_val == 4
// opcode: srli ; op1:x10; dest:x11; op1val:0x200000;  immval:0x4
TEST_IMM_OP( srli, x11, x10, 0x20000, 0x200000, 0x4, x1, 116, x2)

inst_46:
// rs1_val == 1048576, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x100000;  immval:0x9
TEST_IMM_OP( srli, x11, x10, 0x800, 0x100000, 0x9, x1, 120, x2)

inst_47:
// rs1_val == 524288, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x80000;  immval:0xb
TEST_IMM_OP( srli, x11, x10, 0x100, 0x80000, 0xb, x1, 124, x2)

inst_48:
// rs1_val == 131072, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x20000;  immval:0x10
TEST_IMM_OP( srli, x11, x10, 0x2, 0x20000, 0x10, x1, 128, x2)

inst_49:
// rs1_val == 65536, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x10000;  immval:0x0
TEST_IMM_OP( srli, x11, x10, 0x10000, 0x10000, 0x0, x1, 132, x2)

inst_50:
// rs1_val == 32768, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x8000;  immval:0x10
TEST_IMM_OP( srli, x11, x10, 0x0, 0x8000, 0x10, x1, 136, x2)

inst_51:
// rs1_val == 16384, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x4000;  immval:0x6
TEST_IMM_OP( srli, x11, x10, 0x100, 0x4000, 0x6, x1, 140, x2)

inst_52:
// rs1_val == 8192, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x2000;  immval:0x4
TEST_IMM_OP( srli, x11, x10, 0x200, 0x2000, 0x4, x1, 144, x2)

inst_53:
// rs1_val == 4096, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x1000;  immval:0xf
TEST_IMM_OP( srli, x11, x10, 0x0, 0x1000, 0xf, x1, 148, x2)

inst_54:
// rs1_val == 2048, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x800;  immval:0x8
TEST_IMM_OP( srli, x11, x10, 0x8, 0x800, 0x8, x1, 152, x2)

inst_55:
// rs1_val == 1024, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x400;  immval:0x12
TEST_IMM_OP( srli, x11, x10, 0x0, 0x400, 0x12, x1, 156, x2)

inst_56:
// rs1_val == 512, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x200;  immval:0xe
TEST_IMM_OP( srli, x11, x10, 0x0, 0x200, 0xe, x1, 160, x2)

inst_57:
// rs1_val == 256, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x100;  immval:0x13
TEST_IMM_OP( srli, x11, x10, 0x0, 0x100, 0x13, x1, 164, x2)

inst_58:
// rs1_val == 128, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x80;  immval:0x8
TEST_IMM_OP( srli, x11, x10, 0x0, 0x80, 0x8, x1, 168, x2)

inst_59:
// rs1_val == 32, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x20;  immval:0xb
TEST_IMM_OP( srli, x11, x10, 0x0, 0x20, 0xb, x1, 172, x2)

inst_60:
// rs1_val == 16, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x10;  immval:0x17
TEST_IMM_OP( srli, x11, x10, 0x0, 0x10, 0x17, x1, 176, x2)

inst_61:
// rs1_val == 8, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x8;  immval:0x1d
TEST_IMM_OP( srli, x11, x10, 0x0, 0x8, 0x1d, x1, 180, x2)

inst_62:
// rs1_val == 4, rs1_val==4
// opcode: srli ; op1:x10; dest:x11; op1val:0x4;  immval:0x9
TEST_IMM_OP( srli, x11, x10, 0x0, 0x4, 0x9, x1, 184, x2)

inst_63:
// rs1_val == 2, rs1_val==2
// opcode: srli ; op1:x10; dest:x11; op1val:0x2;  immval:0x11
TEST_IMM_OP( srli, x11, x10, 0x0, 0x2, 0x11, x1, 188, x2)

inst_64:
// rs1_val == 1, rs1_val == 1 and imm_val >= 0 and imm_val < xlen, rs1_val > 0 and imm_val == (xlen-1)
// opcode: srli ; op1:x10; dest:x11; op1val:0x1;  immval:0x1f
TEST_IMM_OP( srli, x11, x10, 0x0, 0x1, 0x1f, x1, 192, x2)

inst_65:
// rs1_val==46341, 
// opcode: srli ; op1:x10; dest:x11; op1val:0xb505;  immval:0xd
TEST_IMM_OP( srli, x11, x10, 0x5, 0xb505, 0xd, x1, 196, x2)

inst_66:
// rs1_val==-46339, 
// opcode: srli ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x7
TEST_IMM_OP( srli, x11, x10, 0x1fffe95, -0xb503, 0x7, x1, 200, x2)

inst_67:
// rs1_val==1717986919, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x66666667;  immval:0xb
TEST_IMM_OP( srli, x11, x10, 0xccccc, 0x66666667, 0xb, x1, 204, x2)

inst_68:
// rs1_val==858993460, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x33333334;  immval:0xe
TEST_IMM_OP( srli, x11, x10, 0xcccc, 0x33333334, 0xe, x1, 208, x2)

inst_69:
// rs1_val==6, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x6;  immval:0xe
TEST_IMM_OP( srli, x11, x10, 0x0, 0x6, 0xe, x1, 212, x2)

inst_70:
// rs1_val==-1431655765, 
// opcode: srli ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x1
TEST_IMM_OP( srli, x11, x10, 0x55555555, -0x55555555, 0x1, x1, 216, x2)

inst_71:
// rs1_val==1431655766, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x10
TEST_IMM_OP( srli, x11, x10, 0x5555, 0x55555556, 0x10, x1, 220, x2)

inst_72:
// rs1_val==46339, 
// opcode: srli ; op1:x10; dest:x11; op1val:0xb503;  immval:0x15
TEST_IMM_OP( srli, x11, x10, 0x0, 0xb503, 0x15, x1, 224, x2)

inst_73:
// rs1_val==0, rs1_val == 0 and imm_val >= 0 and imm_val < xlen
// opcode: srli ; op1:x10; dest:x11; op1val:0x0;  immval:0x17
TEST_IMM_OP( srli, x11, x10, 0x0, 0x0, 0x17, x1, 228, x2)

inst_74:
// rs1_val==3, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x3;  immval:0x8
TEST_IMM_OP( srli, x11, x10, 0x0, 0x3, 0x8, x1, 232, x2)

inst_75:
// rs1_val == -1431655766, rs1_val==-1431655766
// opcode: srli ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x2
TEST_IMM_OP( srli, x11, x10, 0x2aaaaaaa, -0x55555556, 0x2, x1, 236, x2)

inst_76:
// rs1_val == 1431655765, rs1_val==1431655765
// opcode: srli ; op1:x10; dest:x11; op1val:0x55555555;  immval:0xb
TEST_IMM_OP( srli, x11, x10, 0xaaaaa, 0x55555555, 0xb, x1, 240, x2)

inst_77:
// rs1_val == imm_val and imm_val > 0 and imm_val < xlen, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x4;  immval:0x4
TEST_IMM_OP( srli, x11, x10, 0x0, 0x4, 0x4, x1, 244, x2)

inst_78:
// rs1_val==1717986917, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x15
TEST_IMM_OP( srli, x11, x10, 0x333, 0x66666665, 0x15, x1, 248, x2)

inst_79:
// rs1_val==858993458, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x6
TEST_IMM_OP( srli, x11, x10, 0xcccccc, 0x33333332, 0x6, x1, 252, x2)

inst_80:
// rs1_val==1431655764, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x6
TEST_IMM_OP( srli, x11, x10, 0x1555555, 0x55555554, 0x6, x1, 256, x2)

inst_81:
// rs1_val==46340, 
// opcode: srli ; op1:x10; dest:x11; op1val:0xb504;  immval:0x17
TEST_IMM_OP( srli, x11, x10, 0x0, 0xb504, 0x17, x1, 260, x2)

inst_82:
// rs1_val==-46340, 
// opcode: srli ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x8
TEST_IMM_OP( srli, x11, x10, 0xffff4a, -0xb504, 0x8, x1, 264, x2)

inst_83:
// rs1_val==1717986918, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x9
TEST_IMM_OP( srli, x11, x10, 0x333333, 0x66666666, 0x9, x1, 268, x2)

inst_84:
// rs1_val==858993459, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x1e
TEST_IMM_OP( srli, x11, x10, 0x0, 0x33333333, 0x1e, x1, 272, x2)

inst_85:
// rs1_val==5, 
// opcode: srli ; op1:x10; dest:x11; op1val:0x5;  immval:0xb
TEST_IMM_OP( srli, x11, x10, 0x0, 0x5, 0xb, x1, 276, x2)

inst_86:
// rs1_val == -1073741825, imm_val == 23
// opcode: srli ; op1:x10; dest:x11; op1val:-0x40000001;  immval:0x17
TEST_IMM_OP( srli, x11, x10, 0x17f, -0x40000001, 0x17, x1, 280, x2)

inst_87:
// rs1_val == -1048577, 
// opcode: srli ; op1:x10; dest:x11; op1val:-0x100001;  immval:0xc
TEST_IMM_OP( srli, x11, x10, 0xffeff, -0x100001, 0xc, x1, 284, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END

RVMODEL_DATA_BEGIN


signature_x1_0:
    .fill 0*(XLEN/32),4,0xdeadbeef


signature_x1_1:
    .fill 8*(XLEN/32),4,0xdeadbeef


signature_x4_0:
    .fill 8*(XLEN/32),4,0xdeadbeef


signature_x1_2:
    .fill 72*(XLEN/32),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*(XLEN/32),4,0xdeadbeef

#endif

RVMODEL_DATA_END