// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version   : 0.5.1
// timestamp : Mon Aug  2 08:58:53 2021 GMT
// usage     : riscv_ctg \
//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
//                  --base-isa rv32e \
//                  --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the jalr instruction of the RISC-V E extension for the jalr covergroup.
// 
#define RVTEST_E
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32E")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",jalr)

RVTEST_SIGBASE( x1,signature_x1_1)

inst_0:
// rs1 != rd, rs1==x8, rd==x12, imm_val < 0, imm_val == -129
// opcode: jalr; op1:x8; dest:x12; immval:-0x81; align:0 
TEST_JALR_OP(x6, x12, x8, -0x81, x1, 0,0)

inst_1:
// rs1 == rd, rs1==x5, rd==x5, imm_val == 2047, imm_val > 0
// opcode: jalr; op1:x5; dest:x5; immval:0x7ff; align:0 
TEST_JALR_OP(x6, x5, x5, 0x7ff, x1, 4,0)

inst_2:
// rs1==x3, rd==x15, imm_val == -1025, 
// opcode: jalr; op1:x3; dest:x15; immval:-0x401; align:0 
TEST_JALR_OP(x6, x15, x3, -0x401, x1, 8,0)

inst_3:
// rs1==x2, rd==x3, imm_val == -513, 
// opcode: jalr; op1:x2; dest:x3; immval:-0x201; align:0 
TEST_JALR_OP(x6, x3, x2, -0x201, x1, 12,0)

inst_4:
// rs1==x4, rd==x9, imm_val == -257, 
// opcode: jalr; op1:x4; dest:x9; immval:-0x101; align:0 
TEST_JALR_OP(x6, x9, x4, -0x101, x1, 16,0)

inst_5:
// rs1==x9, rd==x7, imm_val == -65, 
// opcode: jalr; op1:x9; dest:x7; immval:-0x41; align:0 
TEST_JALR_OP(x6, x7, x9, -0x41, x1, 20,0)

inst_6:
// rs1==x10, rd==x13, imm_val == -33, 
// opcode: jalr; op1:x10; dest:x13; immval:-0x21; align:0 
TEST_JALR_OP(x6, x13, x10, -0x21, x1, 24,0)

inst_7:
// rs1==x14, rd==x0, imm_val == -17, 
// opcode: jalr; op1:x14; dest:x0; immval:-0x11; align:0 
TEST_JALR_OP(x5, x0, x14, -0x11, x1, 28,0)
RVTEST_SIGBASE( x3,signature_x3_0)

inst_8:
// rs1==x15, rd==x4, imm_val == -9, 
// opcode: jalr; op1:x15; dest:x4; immval:-0x9; align:0 
TEST_JALR_OP(x5, x4, x15, -0x9, x3, 0,0)

inst_9:
// rs1==x7, rd==x14, imm_val == -5, 
// opcode: jalr; op1:x7; dest:x14; immval:-0x5; align:0 
TEST_JALR_OP(x5, x14, x7, -0x5, x3, 4,0)

inst_10:
// rs1==x11, rd==x2, imm_val == -3, 
// opcode: jalr; op1:x11; dest:x2; immval:-0x3; align:0 
TEST_JALR_OP(x5, x2, x11, -0x3, x3, 8,0)

inst_11:
// rs1==x6, rd==x11, imm_val == -2, 
// opcode: jalr; op1:x6; dest:x11; immval:-0x2; align:0 
TEST_JALR_OP(x5, x11, x6, -0x2, x3, 12,0)

inst_12:
// rs1==x12, rd==x8, imm_val == -2048, 
// opcode: jalr; op1:x12; dest:x8; immval:-0x800; align:0 
TEST_JALR_OP(x5, x8, x12, -0x800, x3, 16,0)

inst_13:
// rs1==x13, rd==x1, imm_val == 1024, 
// opcode: jalr; op1:x13; dest:x1; immval:0x400; align:0 
TEST_JALR_OP(x5, x1, x13, 0x400, x3, 20,0)

inst_14:
// rs1==x1, rd==x10, imm_val == 512, 
// opcode: jalr; op1:x1; dest:x10; immval:0x200; align:0 
TEST_JALR_OP(x2, x10, x1, 0x200, x3, 24,0)
RVTEST_SIGBASE( x1,signature_x1_2)

inst_15:
// rd==x6, imm_val == 256, 
// opcode: jalr; op1:x13; dest:x6; immval:0x100; align:0 
TEST_JALR_OP(x2, x6, x13, 0x100, x1, 0,0)

inst_16:
// imm_val == 128, 
// opcode: jalr; op1:x10; dest:x11; immval:0x80; align:0 
TEST_JALR_OP(x2, x11, x10, 0x80, x1, 4,0)

inst_17:
// imm_val == 64, 
// opcode: jalr; op1:x10; dest:x11; immval:0x40; align:0 
TEST_JALR_OP(x2, x11, x10, 0x40, x1, 8,0)

inst_18:
// imm_val == 32, 
// opcode: jalr; op1:x10; dest:x11; immval:0x20; align:0 
TEST_JALR_OP(x2, x11, x10, 0x20, x1, 12,0)

inst_19:
// imm_val == 16, 
// opcode: jalr; op1:x10; dest:x11; immval:0x10; align:0 
TEST_JALR_OP(x2, x11, x10, 0x10, x1, 16,0)

inst_20:
// imm_val == 8, 
// opcode: jalr; op1:x10; dest:x11; immval:0x8; align:0 
TEST_JALR_OP(x2, x11, x10, 0x8, x1, 20,0)

inst_21:
// imm_val == 4, 
// opcode: jalr; op1:x10; dest:x11; immval:0x4; align:0 
TEST_JALR_OP(x2, x11, x10, 0x4, x1, 24,0)

inst_22:
// imm_val == 1, 
// opcode: jalr; op1:x10; dest:x11; immval:0x1; align:0 
TEST_JALR_OP(x2, x11, x10, 0x1, x1, 28,0)

inst_23:
// imm_val == -1366, 
// opcode: jalr; op1:x10; dest:x11; immval:-0x556; align:0 
TEST_JALR_OP(x2, x11, x10, -0x556, x1, 32,0)

inst_24:
// imm_val == 1365, 
// opcode: jalr; op1:x10; dest:x11; immval:0x555; align:0 
TEST_JALR_OP(x2, x11, x10, 0x555, x1, 36,0)

inst_25:
// imm_val == 2, 
// opcode: jalr; op1:x10; dest:x11; immval:0x2; align:0 
TEST_JALR_OP(x2, x11, x10, 0x2, x1, 40,0)

inst_26:
// imm_val == -17, 
// opcode: jalr; op1:x10; dest:x11; immval:-0x11; align:0 
TEST_JALR_OP(x2, x11, x10, -0x11, x1, 44,0)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END

RVMODEL_DATA_BEGIN


signature_x1_0:
    .fill 0*(XLEN/32),4,0xdeadbeef


signature_x1_1:
    .fill 8*(XLEN/32),4,0xdeadbeef


signature_x3_0:
    .fill 7*(XLEN/32),4,0xdeadbeef


signature_x1_2:
    .fill 12*(XLEN/32),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*(XLEN/32),4,0xdeadbeef

#endif

RVMODEL_DATA_END