# CORE-V Wally Test Plan

CORE-V Wally is tested in the following ways:

* Run [RISC-V Architecture Compatibility Tests](https://github.com/riscv-non-isa/riscv-arch-test) in lock-step against the ImperasDV reference model.
* Run custom tests to cover virtual memory, PMP, privileged unit, and peripherals in lock step against ImperasDV.
* ***pending: Run random tests generated by risc-dv
* Run CoreMark and Embench benchmarks.
* Run performance validation against reference models for the branch predictor and caches.
* Run the TestFloat suite against all precisions of all operations for the FPU unit.
* *** 83.5% coverage of statements, branches, expressions, and FSM states and transitions
* Boot Buildroot Linux in lock-step against ImperasDV.
* Boot Buildroot Linux on an FPGA and run programs.

# Running Tests

# 

# Detailed Test Plans

The test plans for specific units are lined below:

* Privileged Unit
* Memory Management Unit
* Peripherals
* Branch Predictor Performance Validation
* Cache Performance Validation

Wally is described in an upcoming textbook, *RISC-V System-on-Chip Design*, by Harris, Stine, Thompson, and Harris.