// ----------- // This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg) // version : 0.5.1 // timestamp : Wed Aug 4 06:39:00 2021 GMT // usage : riscv_ctg \ // --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \ // --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \ // --base-isa rv32e \ // --randomize // ----------- // // ----------- // Copyright (c) 2020. RISC-V International. All rights reserved. // SPDX-License-Identifier: BSD-3-Clause // ----------- // // This assembly file tests the c.lui instruction of the RISC-V C extension for the clui covergroup. // #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32EC") .section .text.init .globl rvtest_entry_point rvtest_entry_point: RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",clui) RVTEST_SIGBASE( x2,signature_x2_1) inst_0: // rd==x8, rs1_val < 0 and imm_val < 32 and imm_val !=0 , imm_val == 4 // opcode:c.lui; op1:x8; dest:x8 op1val:-0x1000001; immval:0x4 TEST_CI_OP( c.lui, x8, 0x4000, -0x1000001, 0x4, x2, 0, x5) inst_1: // rd==x10, imm_val == 31, // opcode:c.lui; op1:x10; dest:x10 op1val:-0x4; immval:0x1f TEST_CI_OP( c.lui, x10, 0x1f000, -0x4, 0x1f, x2, 4, x5) inst_2: // rd==x6, imm_val == 47, rs1_val > 0 and imm_val > 32 // opcode:c.lui; op1:x6; dest:x6 op1val:0x4000; immval:0xfffef TEST_CI_OP( c.lui, x6, -0x11000, 0x4000, 0xfffef, x2, 8, x5) inst_3: // rd==x9, imm_val == 55, rs1_val < 0 and imm_val > 32 // opcode:c.lui; op1:x9; dest:x9 op1val:-0x3; immval:0xffff7 TEST_CI_OP( c.lui, x9, -0x9000, -0x3, 0xffff7, x2, 12, x5) inst_4: // rd==x15, imm_val == 59, // opcode:c.lui; op1:x15; dest:x15 op1val:0x4; immval:0xffffb TEST_CI_OP( c.lui, x15, -0x5000, 0x4, 0xffffb, x2, 16, x5) inst_5: // rd==x1, imm_val == 61, // opcode:c.lui; op1:x1; dest:x1 op1val:-0x20000001; immval:0xffffd TEST_CI_OP( c.lui, x1, -0x3000, -0x20000001, 0xffffd, x2, 20, x5) inst_6: // rd==x0, imm_val == 62, // opcode:c.lui; op1:x0; dest:x0 op1val:-0x20000001; immval:0xffffe TEST_CI_OP( c.lui, x0, 0, -0x20000001, 0xffffe, x2, 24, x5) inst_7: // rd==x7, imm_val == 32, // opcode:c.lui; op1:x7; dest:x7 op1val:0x4000; immval:0xfffe0 TEST_CI_OP( c.lui, x7, -0x20000, 0x4000, 0xfffe0, x2, 28, x5) inst_8: // rd==x3, rs1_val > 0 and imm_val < 32 and imm_val !=0 , // opcode:c.lui; op1:x3; dest:x3 op1val:0x10; immval:0xc TEST_CI_OP( c.lui, x3, 0xc000, 0x10, 0xc, x2, 32, x5) inst_9: // rd==x4, imm_val == 16, // opcode:c.lui; op1:x4; dest:x4 op1val:0x7fffffff; immval:0x10 TEST_CI_OP( c.lui, x4, 0x10000, 0x7fffffff, 0x10, x2, 36, x5) inst_10: // rd==x11, imm_val == 8, // opcode:c.lui; op1:x11; dest:x11 op1val:-0x20001; immval:0x8 TEST_CI_OP( c.lui, x11, 0x8000, -0x20001, 0x8, x2, 40, x5) inst_11: // rd==x12, imm_val == 2, // opcode:c.lui; op1:x12; dest:x12 op1val:0x200000; immval:0x2 TEST_CI_OP( c.lui, x12, 0x2000, 0x200000, 0x2, x2, 44, x5) inst_12: // rd==x13, imm_val == 1, // opcode:c.lui; op1:x13; dest:x13 op1val:-0x2001; immval:0x1 TEST_CI_OP( c.lui, x13, 0x1000, -0x2001, 0x1, x2, 48, x3) RVTEST_SIGBASE( x1,signature_x1_0) inst_13: // rd==x14, imm_val == 42, // opcode:c.lui; op1:x14; dest:x14 op1val:0x400000; immval:0xfffea TEST_CI_OP( c.lui, x14, -0x16000, 0x400000, 0xfffea, x1, 0, x3) inst_14: // rd==x5, imm_val == 21, // opcode:c.lui; op1:x5; dest:x5 op1val:-0x10001; immval:0x15 TEST_CI_OP( c.lui, x5, 0x15000, -0x10001, 0x15, x1, 4, x3) #endif RVTEST_CODE_END RVMODEL_HALT RVTEST_DATA_BEGIN .align 4 rvtest_data: .word 0xbabecafe RVTEST_DATA_END RVMODEL_DATA_BEGIN signature_x2_0: .fill 0*(XLEN/32),4,0xdeadbeef signature_x2_1: .fill 13*(XLEN/32),4,0xdeadbeef signature_x1_0: .fill 2*(XLEN/32),4,0xdeadbeef #ifdef rvtest_mtrap_routine mtrap_sigptr: .fill 64*(XLEN/32),4,0xdeadbeef #endif #ifdef rvtest_gpr_save gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif RVMODEL_DATA_END