/////////////////////////////////////////// // // WALLY-MMU // // Author: Kip Macsai-Goren // // Created 2022-02-18 // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // // Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation // files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, // modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software // is furnished to do so, subject to the following conditions: // // The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. // // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES // OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS // BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// #include "WALLY-TEST-LIB-32.h" RVTEST_ISA("RV32I") RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",misa) INIT_TESTS TRAP_HANDLER m // Test 5.3.2.2: Machine ISA register test // Misa is a specific case *** so I don't want to add a whole test case for reading nonzero but unkown value CSRs. csrr x30, misa // should not cause a fault in machine mode. *** not writing to output because MISA is different for different configs. li x7, 0x111 // success value for read of nonzero misa bnez x30, misa_nonzero li x7, 0xbad // misa was zero, store bad value misa_nonzero: sw x7, 0(x6) addi x6, x6, 4 addi x16, x16, 4 END_TESTS TEST_STACK_AND_DATA