/////////////////////////////////////////// // privpiperegs.sv // // Written: David_Harris@hmc.edu 12 May 2022 // Modified: // // Purpose: Pipeline registers for early exceptions // // A component of the Wally configurable RISC-V project. // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // // MIT LICENSE // Permission is hereby granted, free of charge, to any person obtaining a copy of this // software and associated documentation files (the "Software"), to deal in the Software // without restriction, including without limitation the rights to use, copy, modify, merge, // publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons // to whom the Software is furnished to do so, subject to the following conditions: // // The above copyright notice and this permission notice shall be included in all copies or // substantial portions of the Software. // // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, // INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR // PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS // BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, // TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE // OR OTHER DEALINGS IN THE SOFTWARE. //////////////////////////////////////////////////////////////////////////////////////////////// `include "wally-config.vh" module privpiperegs ( input logic clk, reset, input logic StallD, StallE, StallM, input logic FlushD, FlushE, FlushM, input logic InstrPageFaultF, InstrAccessFaultF, input logic IllegalIEUInstrFaultD, output logic InstrPageFaultM, InstrAccessFaultM, output logic IllegalIEUInstrFaultM ); logic InstrPageFaultD, InstrAccessFaultD; logic InstrPageFaultE, InstrAccessFaultE; logic IllegalIEUInstrFaultE; // pipeline fault signals flopenrc #(2) faultregD(clk, reset, FlushD, ~StallD, {InstrPageFaultF, InstrAccessFaultF}, {InstrPageFaultD, InstrAccessFaultD}); flopenrc #(3) faultregE(clk, reset, FlushE, ~StallE, {IllegalIEUInstrFaultD, InstrPageFaultD, InstrAccessFaultD}, {IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE}); flopenrc #(3) faultregM(clk, reset, FlushM, ~StallM, {IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE}, {IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM}); endmodule