Imperas riscvOVPsimPlus riscvOVPsimPlus (64-Bit) v20210329.0 Open Virtual Platform simulator from www.IMPERAS.com. Copyright (c) 2005-2021 Imperas Software Ltd. Contains Imperas Proprietary Information. Licensed Software, All Rights Reserved. Visit www.IMPERAS.com for multicore debug, verification and analysis solutions. riscvOVPsimPlus started: Wed May 12 17:55:33 2021 Info (GDBT_PORT) Host: Tera.Eng.HMC.Edu, Port: 55460 Info (DBC_LGDB) Starting Debugger /cad/riscv/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscv-none-embed-gdb Info (GDBT_WAIT) Waiting for remote debugger to connect... Info (OR_OF) Target 'riscvOVPsim/cpu' has object file read from 'coremark.bare.riscv' Info (OR_PH) Program Headers: Info (OR_PH) Type Offset VirtAddr PhysAddr Info (OR_PH) FileSiz MemSiz Flags Align Info (OR_PD) LOAD 0x0000000000001000 0x0000000080000000 0x0000000080000000 Info (OR_PD) 0x0000000000000204 0x0000000000000204 R-E 1000 Info (OR_PD) LOAD 0x0000000000002000 0x0000000080001000 0x0000000080001000 Info (OR_PD) 0x00000000000047e0 0x0000000000004ff0 RWE 1000 Info (GDBT_CONNECTED) Client connected Info (GDBT_GON) Client disappeared 'riscvOVPsim/cpu' Info Info --------------------------------------------------- Info CPU 'riscvOVPsim/cpu' STATISTICS Info Type : riscv (RV64GC) Info Nominal MIPS : 100 Info Final program counter : 0x80003558 Info Simulated instructions: 1,455,608 Info Simulated MIPS : 0.0 Info --------------------------------------------------- Info Info --------------------------------------------------- Info SIMULATION TIME STATISTICS Info Simulated time : 0.02 seconds Info User time : 99.23 seconds Info System time : 254.08 seconds Info Elapsed time : 1107.49 seconds Info --------------------------------------------------- riscvOVPsimPlus finished: Wed May 12 18:14:04 2021 riscvOVPsimPlus (64-Bit) v20210329.0 Open Virtual Platform simulator from www.IMPERAS.com. Visit www.IMPERAS.com for multicore debug, verification and analysis solutions.