From 39fd199538a37496571f2034a6c0c23011ecf827 Mon Sep 17 00:00:00 2001 From: James Stine Date: Thu, 10 Feb 2022 17:56:27 -0600 Subject: [PATCH 1/3] Slight tweaks to synthDC for library variables --- synthDC/.synopsys_dc.setup | 2 +- synthDC/README.md | 15 ++++++--------- 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup index 22884084..6cc7cec7 100755 --- a/synthDC/.synopsys_dc.setup +++ b/synthDC/.synopsys_dc.setup @@ -12,7 +12,7 @@ if { [info exists ::env(RISCV)] } { } if {$tech == "sky130"} { - set s8lib ../addins/sky130_osu_sc_t12/12T_ms/lib/ + set s8lib $timing_lib/sky130_osu_sc_t12/12T_ms/lib/ lappend search_path $s8lib } elseif {$tech == "sky90"} { set s9lib $timing_lib/sky90/tech_files/ diff --git a/synthDC/README.md b/synthDC/README.md index 7f257b6d..91804b29 100644 --- a/synthDC/README.md +++ b/synthDC/README.md @@ -16,21 +16,18 @@ FREQ Frequency in MHz. Default is 500 CONFIG - The wally configuration file. Default is rv32e. - Examples. - rv32e - rv64gc - rv32gc + The Wally configuration file. The default is rv32e. + Examples: rv32e, rv64gc, rv32gc TECH - The target standard cell library. Default is 130. + The target standard cell library. The default is sky130. sky90: skywater 90nm TT 25C sky130: skywater 130nm TT 25C SAIFPOWER - Controls if power analysis is driven by switching factor or RTL modelsim simulation. - When enabled requires a saif file named power.saif. - Default is 0. + Controls if power analysis is driven by switching factor or + RTL modelsim simulation. When enabled requires a saif file + named power.saif. The default is 0. 0: switching factor power analysis 1: RTL simulation driven power analysis. From 4749941a228e76531388649ee83b5f928267ee02 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 11 Feb 2022 00:20:23 +0000 Subject: [PATCH 2/3] Waive some synthesis warning messages --- synthDC/scripts/synth.tcl | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index adcbe854..2e6da670 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -3,6 +3,12 @@ # james.stine@okstate.edu 27 Sep 2015 # +# Ignore unnecessary warnings: +# intraassignment delays for nonblocking assignments are ignored +suppress_message {VER-130} +# statements in initial blocks are ignored +suppress_message {VER-281} +suppress_message {VER-173} # get outputDir from environment (Makefile) set outputDir $::env(OUTPUTDIR) @@ -336,5 +342,4 @@ redirect $filename { report_constraint } set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_hier.rep"] redirect $filename { report_hierarchy } -#Quit -#quit +quit From de5e80696d7c11ef115490a65b843668075ca3d9 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 11 Feb 2022 01:15:16 +0000 Subject: [PATCH 3/3] Cleaned up synthesis warnings --- pipelined/src/cache/cachefsm.sv | 2 +- pipelined/src/ebu/ahblite.sv | 9 +++------ pipelined/src/ieu/controller.sv | 2 +- pipelined/src/ifu/spillsupport.sv | 2 +- pipelined/src/lsu/busfsm.sv | 2 +- pipelined/src/lsu/interlockfsm.sv | 2 +- pipelined/src/mmu/hptw.sv | 2 +- pipelined/src/uncore/uartPC16550D.sv | 2 +- synthDC/.synopsys_dc.setup | 4 ++-- synthDC/scripts/synth.tcl | 3 --- 10 files changed, 12 insertions(+), 18 deletions(-) diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 054e3d4b..4a22b9cb 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -86,7 +86,7 @@ module cachefsm logic DoAMOMiss, DoReadMiss, DoWriteMiss; logic FlushFlag; - typedef enum {STATE_READY, + typedef enum logic [3:0] {STATE_READY, STATE_MISS_FETCH_WDV, STATE_MISS_FETCH_DONE, diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv index e9f54cbc..9b82aff4 100644 --- a/pipelined/src/ebu/ahblite.sv +++ b/pipelined/src/ebu/ahblite.sv @@ -35,10 +35,6 @@ `include "wally-config.vh" -package ahbliteState; - typedef enum logic [3:0] {IDLE, MEMREAD, MEMWRITE, INSTRREAD} statetype; -endpackage - module ahblite ( input logic clk, reset, // Load control @@ -75,6 +71,9 @@ module ahblite ( (* mark_debug = "true" *) output logic HWRITED ); + typedef enum logic [1:0] {IDLE, MEMREAD, MEMWRITE, INSTRREAD} statetype; + statetype BusState, NextBusState; + logic GrantData; logic [31:0] AccessAddress; logic [2:0] ISize; @@ -88,8 +87,6 @@ module ahblite ( // Data accesses have priority over instructions. However, if a data access comes // while an instruction read is occuring, the instruction read finishes before // the data access can take place. - import ahbliteState::*; - statetype BusState, NextBusState; flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextBusState, IDLE, BusState); diff --git a/pipelined/src/ieu/controller.sv b/pipelined/src/ieu/controller.sv index bde552ab..8f396757 100644 --- a/pipelined/src/ieu/controller.sv +++ b/pipelined/src/ieu/controller.sv @@ -228,5 +228,5 @@ module controller( assign CSRWritePendingDEM = CSRWriteD | CSRWriteE | CSRWriteM; - assign StoreStallD = MemRWE[0] & (|MemRWD | |AtomicD); + assign StoreStallD = MemRWE[0] & ((|MemRWD) | (|AtomicD)); endmodule diff --git a/pipelined/src/ifu/spillsupport.sv b/pipelined/src/ifu/spillsupport.sv index ff8b9b4f..7dbd4f09 100644 --- a/pipelined/src/ifu/spillsupport.sv +++ b/pipelined/src/ifu/spillsupport.sv @@ -64,7 +64,7 @@ module spillsupport ( assign SpillF = &PCF[$clog2(SPILLTHRESHOLD)+1:1]; - typedef enum {STATE_SPILL_READY, STATE_SPILL_SPILL} statetype; + typedef enum logic [1:0] {STATE_SPILL_READY, STATE_SPILL_SPILL} statetype; (* mark_debug = "true" *) statetype CurrState, NextState; always_ff @(posedge clk) diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv index 86aab3a0..837326d5 100644 --- a/pipelined/src/lsu/busfsm.sv +++ b/pipelined/src/lsu/busfsm.sv @@ -64,7 +64,7 @@ module busfsm #(parameter integer WordCountThreshold, logic UnCachedAccess; - typedef enum {STATE_BUS_READY, + typedef enum logic [2:0] {STATE_BUS_READY, STATE_BUS_FETCH, STATE_BUS_WRITE, STATE_BUS_UNCACHED_WRITE, diff --git a/pipelined/src/lsu/interlockfsm.sv b/pipelined/src/lsu/interlockfsm.sv index 749685cd..d09139b9 100644 --- a/pipelined/src/lsu/interlockfsm.sv +++ b/pipelined/src/lsu/interlockfsm.sv @@ -49,7 +49,7 @@ module interlockfsm output logic IgnoreRequestTrapM); - typedef enum {STATE_T0_READY, + typedef enum logic[2:0] {STATE_T0_READY, STATE_T0_REPLAY, STATE_T3_DTLB_MISS, STATE_T4_ITLB_MISS, diff --git a/pipelined/src/mmu/hptw.sv b/pipelined/src/mmu/hptw.sv index e2bf4a14..123d2694 100644 --- a/pipelined/src/mmu/hptw.sv +++ b/pipelined/src/mmu/hptw.sv @@ -46,7 +46,7 @@ module hptw output logic [2:0] HPTWSize // 32 or 64 bit access. ); - typedef enum {L0_ADR, L0_RD, + typedef enum logic [3:0] {L0_ADR, L0_RD, L1_ADR, L1_RD, L2_ADR, L2_RD, L3_ADR, L3_RD, diff --git a/pipelined/src/uncore/uartPC16550D.sv b/pipelined/src/uncore/uartPC16550D.sv index 8dff4c63..d1f72fde 100644 --- a/pipelined/src/uncore/uartPC16550D.sv +++ b/pipelined/src/uncore/uartPC16550D.sv @@ -55,7 +55,7 @@ module uartPC16550D( ); // transmit and receive states // *** neeed to work on synth warning -- it wants to make enums 32 bits by default - typedef enum {UART_IDLE, UART_ACTIVE, UART_DONE, UART_BREAK} statetype; + typedef enum logic [1:0] {UART_IDLE, UART_ACTIVE, UART_DONE, UART_BREAK} statetype; // Registers logic [10:0] RBR; diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup index 6cc7cec7..95b39b13 100755 --- a/synthDC/.synopsys_dc.setup +++ b/synthDC/.synopsys_dc.setup @@ -12,10 +12,10 @@ if { [info exists ::env(RISCV)] } { } if {$tech == "sky130"} { - set s8lib $timing_lib/sky130_osu_sc_t12/12T_ms/lib/ + set s8lib $timing_lib/sky130_osu_sc_t12/12T_ms/lib lappend search_path $s8lib } elseif {$tech == "sky90"} { - set s9lib $timing_lib/sky90/tech_files/ + set s9lib $timing_lib/sky90/sky90_sc/V1.7.4/lib lappend search_path $s9lib } diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index dfe6baa0..5b21e94e 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -3,7 +3,6 @@ # james.stine@okstate.edu 27 Sep 2015 # -<<<<<<< HEAD # Ignore unnecessary warnings: # intraassignment delays for nonblocking assignments are ignored suppress_message {VER-130} @@ -11,8 +10,6 @@ suppress_message {VER-130} suppress_message {VER-281} suppress_message {VER-173} -======= ->>>>>>> 524ba78808f28905d48c866eec9f8e7badd42ea8 # get outputDir from environment (Makefile) set outputDir $::env(OUTPUTDIR) set cfgName $::env(CONFIG)