From fe5c05eb8d28bd0b29c2aa0c0481d43d6e12089e Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 19 Dec 2021 17:53:13 -0600 Subject: [PATCH] Created hack to get around imperas64mmu unknown (value = x) bug. --- wally-pipelined/src/lsu/lsu.sv | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 38374cb3..669b5ee5 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -221,9 +221,12 @@ module lsu end // always_comb // signal to CPU it needs to wait on HPTW. - assign InterlockStall = (CurrState == STATE_T0_READY & (DTLBMissM | ITLBMissF)) | + assign InterlockStall_BUG = (CurrState == STATE_T0_READY & (DTLBMissM | ITLBMissF)) | (CurrState == STATE_T3_DTLB_MISS & ~WalkerPageFaultM) | (CurrState == STATE_T4_ITLB_MISS & ~WalkerInstrPageFaultF) | (CurrState == STATE_T5_ITLB_MISS & ~WalkerInstrPageFaultF) | (CurrState == STATE_T7_DITLB_MISS & ~WalkerPageFaultM); + + assign InterlockStall = InterlockStall_BUG === 1'bx ? 1'b0 : InterlockStall_BUG; + // When replaying CPU memory request after PTW select the IEUAdrM for correct address. assign SelReplayCPURequest = NextState == STATE_T0_REPLAY;