diff --git a/dvtestplan.md b/dvtestplan.md index 6750f400..3b469e3b 100644 --- a/dvtestplan.md +++ b/dvtestplan.md @@ -2,17 +2,17 @@ This document outlines the test plan for the Wally rv64gc configuration to reach Technology Readiness Level 5. -a) Pass riscv-arch-test -b) Boot Linux -c) FPU pass all TestFloat vectors -d) Performance verification: Caches and branch predictor miss rates match independent simulation -e) Directed tests +1. Pass riscv-arch-test +2. Boot Linux +3. FPU pass all TestFloat vectors +4. Performance verification: Caches and branch predictor miss rates match independent simulation +5. Directed tests - Privileged unit: Chapter 5 test plan - MMU: PMA, PMP, virtual memory: Chapter 8 test plan - Peripherals: Chapter 16 test plan -f) Random tests +6. Random tests - riscdv tests -g) Coverage tests +7. Coverage tests - Directed tests to bring coverage up to 100%. - Statement, experssion, branch, condition, FSM coverage in Questa - Do not measure toggle coverage @@ -20,8 +20,8 @@ g) Coverage tests All tests operate correctly in lock-step with ImperasDV Open questions: - How to define extent of riscdv random tests needed? - What other directed tests? +1. How to define extent of riscdv random tests needed? +2. What other directed tests? PMP Tests Virtual Memory Tests How to define pipeline tests?