From 29f015810b6683322c98f60757ffca739d4d9b24 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 7 Sep 2022 09:37:59 -0700 Subject: [PATCH 1/3] Added rv32i config for regression of wally32periph --- pipelined/regression/regression-wally | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally index 20519bbb..431b297f 100755 --- a/pipelined/regression/regression-wally +++ b/pipelined/regression/regression-wally @@ -82,7 +82,7 @@ for test in tests32gc: grepstr="All tests ran without failures") configs.append(tc) -tests32ic = ["arch32i", "arch32c", "imperas32i", "imperas32c", "wally32periph"] +tests32ic = ["arch32i", "arch32c", "imperas32i", "imperas32c"] for test in tests32ic: tc = TestCase( name=test, @@ -91,6 +91,16 @@ for test in tests32ic: grepstr="All tests ran without failures") configs.append(tc) +tests32i = ["wally32periph"] +for test in tests32i: + tc = TestCase( + name=test, + variant="rv32i", + cmd="vsim > {} -c < Date: Wed, 7 Sep 2022 10:21:27 -0700 Subject: [PATCH 2/3] Preprocessing cleanup --- pipelined/src/fpu/fdivsqrt.sv | 5 ++--- pipelined/src/fpu/fdivsqrtfsm.sv | 3 +-- pipelined/src/fpu/fdivsqrtpreproc.sv | 4 +--- 3 files changed, 4 insertions(+), 8 deletions(-) diff --git a/pipelined/src/fpu/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt.sv index 17f09a7a..7548337f 100644 --- a/pipelined/src/fpu/fdivsqrt.sv +++ b/pipelined/src/fpu/fdivsqrt.sv @@ -61,17 +61,16 @@ module fdivsqrt( logic [`DIVN-2:0] Dpreproc; logic [`DIVb:0] FirstS, FirstSM, FirstQ, FirstQM; logic [`DIVb-1:0] FirstC; - logic [`DURLEN-1:0] Dur; logic NegSticky; logic [`DIVCOPIES-1:0] qn; logic WZero; fdivsqrtpreproc fdivsqrtpreproc( .clk, .DivStart(DivStartE), .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE), - .Sqrt(SqrtE), .Dur, .Ym(YmE), .XZero(XZeroE), .X, .Dpreproc); + .Sqrt(SqrtE), .Ym(YmE), .XZero(XZeroE), .X, .Dpreproc); fdivsqrtfsm fdivsqrtfsm( .reset, .XsE, .SqrtE, - .Dur, .DivBusy, .clk, .DivStart(DivStartE),.StallE, .StallM, .DivDone, .XZeroE, .YZeroE, + .DivBusy, .clk, .DivStart(DivStartE),.StallE, .StallM, .DivDone, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .XInfE, .YInfE, .EarlyTermShiftE(EarlyTermShiftM), .WZero); fdivsqrtiter fdivsqrtiter( diff --git a/pipelined/src/fpu/fdivsqrtfsm.sv b/pipelined/src/fpu/fdivsqrtfsm.sv index c788066e..e7aae109 100644 --- a/pipelined/src/fpu/fdivsqrtfsm.sv +++ b/pipelined/src/fpu/fdivsqrtfsm.sv @@ -41,7 +41,6 @@ module fdivsqrtfsm( input logic SqrtE, input logic StallE, input logic StallM, - input logic [`DURLEN-1:0] Dur, input logic WZero, output logic [`DURLEN-1:0] EarlyTermShiftE, output logic DivDone, @@ -63,7 +62,7 @@ module fdivsqrtfsm( if (reset) begin state <= #1 IDLE; end else if (DivStart&~StallE) begin - step <= Dur; + step <= (`DURLEN)'(`FPDUR); // *** this should be adjusted to depend on the precision if (SpecialCase) state <= #1 DONE; else state <= #1 BUSY; end else if (DivDone) begin diff --git a/pipelined/src/fpu/fdivsqrtpreproc.sv b/pipelined/src/fpu/fdivsqrtpreproc.sv index 0338c2b8..2e383fb2 100644 --- a/pipelined/src/fpu/fdivsqrtpreproc.sv +++ b/pipelined/src/fpu/fdivsqrtpreproc.sv @@ -40,8 +40,7 @@ module fdivsqrtpreproc ( input logic XZero, output logic [`NE+1:0] QeM, output logic [`DIVb:0] X, - output logic [`DIVN-2:0] Dpreproc, - output logic [`DURLEN-1:0] Dur + output logic [`DIVN-2:0] Dpreproc ); // logic [`XLEN-1:0] PosA, PosB; // logic [`DIVLEN-1:0] ExtraA, ExtraB, PreprocA, PreprocB, PreprocX, PreprocY; @@ -73,7 +72,6 @@ module fdivsqrtpreproc ( assign SqrtX = Xe[0]^XZeroCnt[0] ? {1'b0, ~XZero, PreprocX} : {~XZero, PreprocX, 1'b0}; assign X = Sqrt ? {SqrtX, {`DIVb-1-`NF{1'b0}}} : {~XZero, PreprocX, {`DIVb-`NF{1'b0}}}; assign Dpreproc = {PreprocY, {`DIVN-1-`NF{1'b0}}}; - assign Dur = (`DURLEN)'(`FPDUR); // radix 2 radix 4 // 1 copies DIVLEN+2 DIVLEN+2/2 From e01b03e9b2fb5e7bc9f0a9e3265acb073eee8ce1 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 7 Sep 2022 10:26:09 -0700 Subject: [PATCH 3/3] Run 16-bit fsqrt tests first --- pipelined/testbench/testbench-fp.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/testbench/testbench-fp.sv b/pipelined/testbench/testbench-fp.sv index d0f18a68..4e0755e4 100644 --- a/pipelined/testbench/testbench-fp.sv +++ b/pipelined/testbench/testbench-fp.sv @@ -585,7 +585,7 @@ module testbenchfp; end if (TEST === "sqrt" | TEST === "all") begin // if sqrt is being tested // add the correct tests/op-ctrls/unit/fmt to their lists - Tests = {Tests, f16sqrt}; + Tests = {f16sqrt, Tests}; OpCtrl = {OpCtrl, `SQRT_OPCTRL}; WriteInt = {WriteInt, 1'b0}; for(int i = 0; i<5; i++) begin