diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv
index 0b7dd3d0..5f3da09b 100644
--- a/pipelined/src/cache/cachefsm.sv
+++ b/pipelined/src/cache/cachefsm.sv
@@ -193,10 +193,13 @@ module cachefsm
   assign FlushAdrCntRst = (CurrState == STATE_READY);
   assign FlushWayCntRst = (CurrState == STATE_READY) | (CurrState == STATE_FLUSH_INCR);
   // Bus interface controls
-  assign CacheBusRW[1] = (CurrState == STATE_READY & DoAnyMiss) | (CurrState == STATE_MISS_FETCH_WDV & ~CacheBusAck);
+//  assign CacheBusRW[1] = (CurrState == STATE_READY & DoAnyMiss) | (CurrState == STATE_MISS_FETCH_WDV & ~CacheBusAck);
+  assign CacheBusRW[1] = CurrState == STATE_READY & DoAnyMiss;
+//  assign CacheBusRW[0] = (CurrState == STATE_MISS_FETCH_WDV & CacheBusAck & VictimDirty) |
+//                          (CurrState == STATE_MISS_EVICT_DIRTY & ~CacheBusAck) |
+//                          (CurrState == STATE_FLUSH_WRITE_BACK & ~CacheBusAck) |
+//                          (CurrState == STATE_FLUSH_CHECK & VictimDirty);
   assign CacheBusRW[0] = (CurrState == STATE_MISS_FETCH_WDV & CacheBusAck & VictimDirty) |
-                          (CurrState == STATE_MISS_EVICT_DIRTY & ~CacheBusAck) |
-                          (CurrState == STATE_FLUSH_WRITE_BACK & ~CacheBusAck) |
                           (CurrState == STATE_FLUSH_CHECK & VictimDirty);
   // **** can this be simplified?
   assign SelAdr = (CurrState == STATE_READY & (IgnoreRequestTLB & ~TrapM)) | // Ignore Request is needed on TLB miss.
diff --git a/pipelined/src/ebu/buscachefsm.sv b/pipelined/src/ebu/buscachefsm.sv
index 40759c82..106ec678 100644
--- a/pipelined/src/ebu/buscachefsm.sv
+++ b/pipelined/src/ebu/buscachefsm.sv
@@ -141,11 +141,11 @@ module buscachefsm #(parameter integer   WordCountThreshold,
   // AHB bus interface
   assign HTRANS = (CurrState == ADR_PHASE & HREADY & (|BusRW | |CacheBusRW)) |
                   (CurrState == DATA_PHASE & ~HREADY) |
-                  (CacheAccess & ~|WordCount & |CacheBusRW) ? AHB_NONSEQ :
+                  (CacheAccess & ~|WordCount & |CacheBusRW) ? AHB_NONSEQ : // if we have a pipelined request
                   (CacheAccess & |WordCount) ? (`BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE;
 
-  assign HWRITE = BusRW[0] | CacheBusRW[0];
-  assign HBURST = `BURST_EN ? ((|CacheBusRW) ? LocalBurstType : 3'b0) : 3'b0;  // this line is for burst.
+  assign HWRITE = BusRW[0] | CacheBusRW[0] | (CurrState == CACHE_EVICT & |WordCount);
+  assign HBURST = `BURST_EN & (|CacheBusRW | (CacheAccess & |WordCount)) ? LocalBurstType : 3'b0;  
   
   always_comb begin
     case(WordCountThreshold)