diff --git a/pipelined/src/ebu/ahbcacheinterface.sv b/pipelined/src/ebu/ahbcacheinterface.sv index 19b51fe2..a127e0fa 100644 --- a/pipelined/src/ebu/ahbcacheinterface.sv +++ b/pipelined/src/ebu/ahbcacheinterface.sv @@ -1,8 +1,9 @@ /////////////////////////////////////////// // ahbcacheinterface.sv // -// Written: Ross Thompson ross1728@gmail.com August 29, 2022 -// Modified: +// Written: Ross Thompson ross1728@gmail.com +// Created: August 29, 2022 +// Modified: 18 January 2023 // // Purpose: Translates cache bus requests and uncached ieu memory requests into AHB transactions. // @@ -28,7 +29,12 @@ `include "wally-config.vh" -module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, AHBWLOGBWPL, LLENPOVERAHBW) ( +module ahbcacheinterface #( + parameter integer BEATSPERLINE, // Number of AHBW words (beats) in cacheline + parameter integer AHBWLOGBWPL, // Log2 of ^ + parameter integer LINELEN, // Number of bits in cacheline + parameter integer LLENPOVERAHBW // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation) +)( input logic HCLK, HRESETn, // bus interface controls input logic HREADY, // AHB peripheral ready diff --git a/pipelined/src/ebu/buscachefsm.sv b/pipelined/src/ebu/buscachefsm.sv index 0b80d529..97002cab 100644 --- a/pipelined/src/ebu/buscachefsm.sv +++ b/pipelined/src/ebu/buscachefsm.sv @@ -28,7 +28,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// `include "wally-config.vh" -`define BURST_EN 1 +`define BURST_EN 1 // Enables burst mode. Disable to show the lost performance. // HCLK and clk must be the same clock! module buscachefsm #( diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 63cea9b4..c0d8837d 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -227,7 +227,7 @@ module ifu ( .NextAdr(PCNextFSpill[11:0]), .PAdr(PCPF), .CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM)); - ahbcacheinterface #(WORDSPERLINE, LINELEN, LOGBWPL, LLENPOVERAHBW) + ahbcacheinterface #(WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW) ahbcacheinterface(.HCLK(clk), .HRESETn(~reset), .HRDATA, .Flush(FlushD), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(), diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index eb3b8caf..95f058c3 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -242,7 +242,7 @@ module lsu ( localparam integer LLENLOGBWPL = $clog2(LLENWORDSPERLINE); // Log2 of ^ localparam integer BEATSPERLINE = `DCACHE_LINELENINBITS/`AHBW; // Number of AHBW words (beats) in cacheline localparam integer AHBWLOGBWPL = $clog2(BEATSPERLINE); // Log2 of ^ - localparam integer LINELEN = `DCACHE_LINELENINBITS; // Number of bytes in cacheline + localparam integer LINELEN = `DCACHE_LINELENINBITS; // Number of bits in cacheline localparam integer LLENPOVERAHBW = `LLEN / `AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation) logic [LINELEN-1:0] FetchBuffer; // Temporary buffer to hold partially fetched cacheline @@ -273,7 +273,7 @@ module lsu ( .FetchBuffer, .CacheBusRW, .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0)); - ahbcacheinterface #(.BEATSPERLINE(BEATSPERLINE), .LINELEN(LINELEN), .AHBWLOGBWPL(AHBWLOGBWPL), .LLENPOVERAHBW(LLENPOVERAHBW)) ahbcacheinterface( + ahbcacheinterface #(.BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW)) ahbcacheinterface( .HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY),