From fbee4963daa7c27dad9f649247966889f8fb3150 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 25 Oct 2021 11:49:20 -0700 Subject: [PATCH] Converted flops to synchronous reset now that reset signal is synchronized --- wally-pipelined/src/generic/flop/flopenl.sv | 4 +- wally-pipelined/src/generic/flop/flopenr.sv | 4 +- wally-pipelined/src/generic/flop/flopenrc.sv | 4 +- wally-pipelined/src/generic/flop/flopens.sv | 4 +- wally-pipelined/src/generic/flop/flopr.sv | 4 +- wally-pipelined/src/generic/flop/floprc.sv | 10 ++--- .../src/generic/flop/synchronizer.sv | 41 +++++++++++++++++++ 7 files changed, 55 insertions(+), 16 deletions(-) create mode 100644 wally-pipelined/src/generic/flop/synchronizer.sv diff --git a/wally-pipelined/src/generic/flop/flopenl.sv b/wally-pipelined/src/generic/flop/flopenl.sv index acf3f2a0..4361dc4c 100644 --- a/wally-pipelined/src/generic/flop/flopenl.sv +++ b/wally-pipelined/src/generic/flop/flopenl.sv @@ -25,14 +25,14 @@ `include "wally-config.vh" -// flop with enable, asynchronous load +// flop with enable, synchronous load module flopenl #(parameter WIDTH = 8, parameter type TYPE=logic [WIDTH-1:0]) ( input logic clk, load, en, input TYPE d, input TYPE val, output TYPE q); - always_ff @(posedge clk, posedge load) + always_ff @(posedge clk) if (load) q <= #1 val; else if (en) q <= #1 d; endmodule diff --git a/wally-pipelined/src/generic/flop/flopenr.sv b/wally-pipelined/src/generic/flop/flopenr.sv index 9db912ea..a30535d8 100644 --- a/wally-pipelined/src/generic/flop/flopenr.sv +++ b/wally-pipelined/src/generic/flop/flopenr.sv @@ -25,13 +25,13 @@ `include "wally-config.vh" -// flop with enable, asynchronous reset +// flop with enable, synchronous reset module flopenr #(parameter WIDTH = 8) ( input logic clk, reset, en, input logic [WIDTH-1:0] d, output logic [WIDTH-1:0] q); - always_ff @(posedge clk, posedge reset) + always_ff @(posedge clk) if (reset) q <= #1 0; else if (en) q <= #1 d; endmodule diff --git a/wally-pipelined/src/generic/flop/flopenrc.sv b/wally-pipelined/src/generic/flop/flopenrc.sv index d8806196..010a5210 100644 --- a/wally-pipelined/src/generic/flop/flopenrc.sv +++ b/wally-pipelined/src/generic/flop/flopenrc.sv @@ -25,13 +25,13 @@ `include "wally-config.vh" -// flop with enable, asynchronous reset, synchronous clear +// flop with enable, synchronous reset, enabled clear module flopenrc #(parameter WIDTH = 8) ( input logic clk, reset, clear, en, input logic [WIDTH-1:0] d, output logic [WIDTH-1:0] q); - always_ff @(posedge clk, posedge reset) + always_ff @(posedge clk) if (reset) q <= #1 0; else if (en) if (clear) q <= #1 0; diff --git a/wally-pipelined/src/generic/flop/flopens.sv b/wally-pipelined/src/generic/flop/flopens.sv index d51659b8..22c6061c 100644 --- a/wally-pipelined/src/generic/flop/flopens.sv +++ b/wally-pipelined/src/generic/flop/flopens.sv @@ -25,13 +25,13 @@ `include "wally-config.vh" -// flop with enable, asynchronous set +// flop with enable, synchronous set module flopens #(parameter WIDTH = 8) ( input logic clk, set, en, input logic [WIDTH-1:0] d, output logic [WIDTH-1:0] q); - always_ff @(posedge clk, posedge set) + always_ff @(posedge clk) if (set) q <= #1 1; else if (en) q <= #1 d; endmodule diff --git a/wally-pipelined/src/generic/flop/flopr.sv b/wally-pipelined/src/generic/flop/flopr.sv index 5ff6a5a9..e89f28e5 100644 --- a/wally-pipelined/src/generic/flop/flopr.sv +++ b/wally-pipelined/src/generic/flop/flopr.sv @@ -25,13 +25,13 @@ `include "wally-config.vh" -// flop with asynchronous reset +// flop with synchronous reset module flopr #(parameter WIDTH = 8) ( input logic clk, reset, input logic [WIDTH-1:0] d, output logic [WIDTH-1:0] q); - always_ff @(posedge clk, posedge reset) + always_ff @(posedge clk) if (reset) q <= #1 0; else q <= #1 d; endmodule diff --git a/wally-pipelined/src/generic/flop/floprc.sv b/wally-pipelined/src/generic/flop/floprc.sv index 9d5f17c7..27d0076f 100644 --- a/wally-pipelined/src/generic/flop/floprc.sv +++ b/wally-pipelined/src/generic/flop/floprc.sv @@ -25,7 +25,7 @@ `include "wally-config.vh" -// flop with asynchronous reset, synchronous clear +// flop with synchronous reset, synchronous clear module floprc #(parameter WIDTH = 8) ( input logic clk, input logic reset, @@ -33,9 +33,7 @@ module floprc #(parameter WIDTH = 8) ( input logic [WIDTH-1:0] d, output logic [WIDTH-1:0] q); - always_ff @(posedge clk, posedge reset) - if (reset) q <= #1 0; - else - if (clear) q <= #1 0; - else q <= #1 d; + always_ff @(posedge clk) + if (reset | clear ) q <= #1 0; + else q <= #1 d; endmodule diff --git a/wally-pipelined/src/generic/flop/synchronizer.sv b/wally-pipelined/src/generic/flop/synchronizer.sv new file mode 100644 index 00000000..ab4255c1 --- /dev/null +++ b/wally-pipelined/src/generic/flop/synchronizer.sv @@ -0,0 +1,41 @@ +/////////////////////////////////////////// +// synchronizer.sv +// +// Written: David_Harris@hmc.edu 25 October 2021 +// Modified: +// +// Purpose: Two-stage flip-flop synchronizer +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +`include "wally-config.vh" + +// ordinary flip-flop +module synchronizer ( + input logic clk, + input logic d, + output logic q); + + logic mid; + + always_ff @(posedge clk) begin + mid <= #1 d; + q <= #1 d; + end +endmodule +