From 6431e358ca2d14d84805a98e250aef97438e2715 Mon Sep 17 00:00:00 2001
From: David Harris <74973295+davidharrishmc@users.noreply.github.com>
Date: Thu, 6 Apr 2023 09:23:09 -0700
Subject: [PATCH 1/2] Create dvtestplan.md

---
 dvtestplan.md | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)
 create mode 100644 dvtestplan.md

diff --git a/dvtestplan.md b/dvtestplan.md
new file mode 100644
index 00000000..6750f400
--- /dev/null
+++ b/dvtestplan.md
@@ -0,0 +1,30 @@
+# core-v-wally Design Verification Test Plan
+
+This document outlines the test plan for the Wally rv64gc configuration to reach Technology Readiness Level 5.
+
+a) Pass riscv-arch-test
+b) Boot Linux
+c) FPU pass all TestFloat vectors
+d) Performance verification: Caches and branch predictor miss rates match independent simulation
+e) Directed tests
+	- Privileged unit: Chapter 5 test plan
+	- MMU: PMA, PMP, virtual memory: Chapter 8 test plan
+	- Peripherals: Chapter 16 test plan
+f) Random tests
+	- riscdv tests
+g) Coverage tests
+	- Directed tests to bring coverage up to 100%.  
+		- Statement, experssion, branch, condition, FSM coverage in Questa 
+		- Do not measure toggle coverage
+
+All tests operate correctly in lock-step with ImperasDV
+
+Open questions:
+	How to define extent of riscdv random tests needed?
+	What other directed tests?
+    PMP Tests
+    Virtual Memory Tests
+		How to define pipeline tests? 
+			Simple ones like use after load stall are not important.
+			Hard ones such as page table walker fault during data access while I$ access is pending are hard to articulate and code
+      Is there an example of a good directed pipeline test plan & implementation

From fddbd79209eef58beda73f49298528d36d8da69c Mon Sep 17 00:00:00 2001
From: David Harris <74973295+davidharrishmc@users.noreply.github.com>
Date: Thu, 6 Apr 2023 09:29:47 -0700
Subject: [PATCH 2/2] Update dvtestplan.md

---
 dvtestplan.md | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/dvtestplan.md b/dvtestplan.md
index 6750f400..3b469e3b 100644
--- a/dvtestplan.md
+++ b/dvtestplan.md
@@ -2,17 +2,17 @@
 
 This document outlines the test plan for the Wally rv64gc configuration to reach Technology Readiness Level 5.
 
-a) Pass riscv-arch-test
-b) Boot Linux
-c) FPU pass all TestFloat vectors
-d) Performance verification: Caches and branch predictor miss rates match independent simulation
-e) Directed tests
+1. Pass riscv-arch-test
+2. Boot Linux
+3. FPU pass all TestFloat vectors
+4. Performance verification: Caches and branch predictor miss rates match independent simulation
+5. Directed tests
 	- Privileged unit: Chapter 5 test plan
 	- MMU: PMA, PMP, virtual memory: Chapter 8 test plan
 	- Peripherals: Chapter 16 test plan
-f) Random tests
+6. Random tests
 	- riscdv tests
-g) Coverage tests
+7. Coverage tests
 	- Directed tests to bring coverage up to 100%.  
 		- Statement, experssion, branch, condition, FSM coverage in Questa 
 		- Do not measure toggle coverage
@@ -20,8 +20,8 @@ g) Coverage tests
 All tests operate correctly in lock-step with ImperasDV
 
 Open questions:
-	How to define extent of riscdv random tests needed?
-	What other directed tests?
+1. How to define extent of riscdv random tests needed?
+2. What other directed tests?
     PMP Tests
     Virtual Memory Tests
 		How to define pipeline tests?