From f74ecbb81e5b8a94178c40acb67bdb07e0c03df9 Mon Sep 17 00:00:00 2001
From: Ross Thompson <stephen.thompson.37@us.af.mil>
Date: Wed, 23 Jun 2021 15:13:56 -0500
Subject: [PATCH] Updated icache to abhlite to use pa_bits length and moved F/D
stage instr register to ifu from icache.
---
wally-pipelined/src/cache/ICacheCntrl.sv | 11 +++++-----
wally-pipelined/src/cache/icache.sv | 4 ++--
wally-pipelined/src/ebu/ahblite.sv | 2 +-
wally-pipelined/src/ifu/ifu.sv | 20 +++++--------------
.../src/wally/wallypipelinedhart.sv | 2 +-
5 files changed, 14 insertions(+), 25 deletions(-)
diff --git a/wally-pipelined/src/cache/ICacheCntrl.sv b/wally-pipelined/src/cache/ICacheCntrl.sv
index d73a85bc..f290f0ad 100644
--- a/wally-pipelined/src/cache/ICacheCntrl.sv
+++ b/wally-pipelined/src/cache/ICacheCntrl.sv
@@ -52,7 +52,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
output logic CompressedF,
// The instruction that was requested
// If this instruction is compressed, upper 16 bits may be the next 16 bits or may be zeros
- output logic [31:0] InstrRawD,
+ output logic [31:0] FinalInstrRawF,
// Outputs to pipeline control stuff
output logic ICacheStallF, EndFetchState,
@@ -62,7 +62,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
input logic [`XLEN-1:0] InstrInF,
input logic InstrAckF,
// The read we request from main memory
- output logic [`XLEN-1:0] InstrPAdrF,
+ output logic [`PA_BITS-1:0] InstrPAdrF,
output logic InstrReadF
);
@@ -119,6 +119,8 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
localparam WORDSPERLINE = BLOCKLEN/`XLEN;
localparam LOGWPL = $clog2(WORDSPERLINE);
+ localparam integer PA_WIDTH = `PA_BITS - 2;
+
logic [4:0] CurrState, NextState;
logic hit, spill;
@@ -137,8 +139,6 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
logic [`PA_BITS-1:OFFSETWIDTH] PCPTrunkF;
- logic [31:0] FinalInstrRawF;
-
logic [15:0] SpillDataBlock0;
localparam [31:0] NOP = 32'h13;
@@ -156,7 +156,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
// on spill we want to get the first 2 bytes of the next cache block.
// the spill only occurs if the PCPF mod BlockByteLength == -2. Therefore we can
// simply add 2 to land on the next cache block.
- assign PCPSpillF = PCPF + 2'b10; // *** modelsim does not allow the use of PA_BITS for literal width.
+ assign PCPSpillF = PCPF + {{{PA_WIDTH}{1'b0}}, 2'b10}; // *** modelsim does not allow the use of PA_BITS for literal width.
// now we have to select between these three PCs
assign PCPreFinalF = PCMux[0] | StallF ? PCPF : PCNextF; // *** don't like the stallf, but it is necessary
@@ -453,6 +453,5 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
.d(reset),
.q(reset_q));
- flopenl #(32) AlignedInstrRawDFlop(clk, reset | reset_q, ~StallD, FlushD ? NOP : FinalInstrRawF, NOP, InstrRawD);
endmodule
diff --git a/wally-pipelined/src/cache/icache.sv b/wally-pipelined/src/cache/icache.sv
index 907d30fa..abf828fc 100644
--- a/wally-pipelined/src/cache/icache.sv
+++ b/wally-pipelined/src/cache/icache.sv
@@ -37,7 +37,7 @@ module icache
input logic [`XLEN-1:0] InstrInF,
input logic InstrAckF,
// Read requested from the ebu unit
- output logic [`XLEN-1:0] InstrPAdrF,
+ output logic [`PA_BITS-1:0] InstrPAdrF,
output logic InstrReadF,
// High if the instruction currently in the fetch stage is compressed
output logic CompressedF,
@@ -45,7 +45,7 @@ module icache
output logic ICacheStallF,
// The raw (not decompressed) instruction that was requested
// If this instruction is compressed, upper 16 bits may be the next 16 bits or may be zeros
- output logic [31:0] InstrRawD
+ output logic [31:0] FinalInstrRawF
);
// Configuration parameters
diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv
index 88e8f27a..c59dfa9b 100644
--- a/wally-pipelined/src/ebu/ahblite.sv
+++ b/wally-pipelined/src/ebu/ahblite.sv
@@ -42,7 +42,7 @@ module ahblite (
input logic [1:0] AtomicMaskedM,
input logic [6:0] Funct7M,
// Signals from Instruction Cache
- input logic [`XLEN-1:0] InstrPAdrF, // *** rename these to match block diagram
+ input logic [`PA_BITS-1:0] InstrPAdrF, // *** rename these to match block diagram
input logic InstrReadF,
output logic [`XLEN-1:0] InstrRData,
output logic InstrAckF,
diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv
index 54499a5f..afae5ff4 100644
--- a/wally-pipelined/src/ifu/ifu.sv
+++ b/wally-pipelined/src/ifu/ifu.sv
@@ -34,7 +34,7 @@ module ifu (
input logic [`XLEN-1:0] InstrInF,
input logic InstrAckF,
output logic [`XLEN-1:0] PCF,
- output logic [`XLEN-1:0] InstrPAdrF,
+ output logic [`PA_BITS-1:0] InstrPAdrF,
output logic InstrReadF,
output logic ICacheStallF,
// Decode
@@ -92,10 +92,10 @@ module ifu (
logic misaligned, BranchMisalignedFaultE, BranchMisalignedFaultM, TrapMisalignedFaultM;
logic PrivilegedChangePCM;
logic IllegalCompInstrD;
- logic [`XLEN-1:0] PCPlus2or4F, PCW, PCLinkD, PCLinkM, PCNextPF, PCPF;
+ logic [`XLEN-1:0] PCPlus2or4F, PCW, PCLinkD, PCLinkM, PCPF;
logic [`XLEN-3:0] PCPlusUpperF;
logic CompressedF;
- logic [31:0] InstrRawD;
+ logic [31:0] InstrRawD, FinalInstrRawF;
localparam [31:0] nop = 32'h00000013; // instruction for NOP
logic reset_q; // *** look at this later.
@@ -136,17 +136,15 @@ module ifu (
//assign InstrReadF = ~StallD; // *** & ICacheMissF; add later
// assign InstrReadF = 1; // *** & ICacheMissF; add later
- // jarred 2021-03-14 Add instrution cache block to remove rd2
- assign PCNextPF = PCNextF; // Temporary workaround until iTLB is live
icache icache(.*,
.PCNextF(PCNextF[`PA_BITS-1:0]),
.PCPF(PCPFmmu));
+ flopenl #(32) AlignedInstrRawDFlop(clk, reset | reset_q, ~StallD, FlushD ? nop : FinalInstrRawF, nop, InstrRawD);
assign PrivilegedChangePCM = RetM | TrapM;
- //mux3 #(`XLEN) pcmux(PCPlus2or4F, PCCorrectE, PrivilegedNextPCM, {PrivilegedChangePCM, BPPredWrongE}, UnalignedPCNextF);
mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F),
.d1(BPPredPCF),
.s(SelBPPredF),
@@ -162,15 +160,6 @@ module ifu (
.s(PrivilegedChangePCM),
.y(PCNext2F));
- // *** try to remove this in the future as it can add a long path.
- // StallF may arrive late.
-/* -----\/----- EXCLUDED -----\/-----
- mux2 #(`XLEN) pcmux3(.d0(PCNext2F),
- .d1(PCF),
- .s(StallF),
- .y(PCNext3F));
- -----/\----- EXCLUDED -----/\----- */
-
mux2 #(`XLEN) pcmux4(.d0(PCNext2F),
.d1(`RESET_VECTOR),
.s(reset_q),
@@ -255,6 +244,7 @@ module ifu (
// pipeline misaligned faults to M stage
assign BranchMisalignedFaultE = misaligned & PCSrcE; // E-stage (Branch/Jump) misaligned
flopenr #(1) InstrMisalginedReg(clk, reset, ~StallM, BranchMisalignedFaultE, BranchMisalignedFaultM);
+ // *** Ross Thompson. Check InstrMisalignedAdrM as I believe it is the same as PCF. Should be able to remove.
flopenr #(`XLEN) InstrMisalignedAdrReg(clk, reset, ~StallM, PCNextF, InstrMisalignedAdrM);
assign TrapMisalignedFaultM = misaligned & PrivilegedChangePCM;
assign InstrMisalignedFaultM = BranchMisalignedFaultM; // | TrapMisalignedFaultM; *** put this back in without causing a cyclic path
diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv
index 8e71f445..b32770b9 100644
--- a/wally-pipelined/src/wally/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@@ -137,7 +137,7 @@ module wallypipelinedhart (
logic [`XLEN-1:0] MemAdrM, WriteDataM;
logic [`PA_BITS-1:0] MemPAdrM;
logic [`XLEN-1:0] ReadDataW;
- logic [`XLEN-1:0] InstrPAdrF;
+ logic [`PA_BITS-1:0] InstrPAdrF;
logic [`XLEN-1:0] InstrRData;
logic InstrReadF;
logic DataStall;