From f711eb0bcfdb234d19d8af3a0b344c63467b6835 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren <kipmacsaigoren@gmail.com> Date: Tue, 11 Oct 2022 23:08:02 +0000 Subject: [PATCH] quick fix to endianness wapping 64 bit reads in 32 bit confgs --- pipelined/src/lsu/lsu.sv | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 2af5851e..2bab1727 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -350,9 +350,13 @@ module lsu ( // hart works little-endian internally // swap the bytes when read from big-endian memory ///////////////////////////////////////////////////////////////////////////////////////////// + if (`BIGENDIAN_SUPPORTED) begin:endian + logic [`LLEN-1:0] ReadDataWordMuxSwapM; // *** swap the top and bottom XLEN bits based on endianness // Ross doesn't like this + if (`LLEN == 2*`XLEN) assign ReadDataWordMuxSwapM = BigEndianM ? {ReadDataWordMuxM[`XLEN-1:0], ReadDataWordMuxM[`LLEN-1:`XLEN]} : ReadDataWordMuxM; + else assign ReadDataWordMuxSwapM = ReadDataWordMuxM; endianswap #(`LLEN) storeswap(.BigEndianM, .a(LittleEndianWriteDataM), .y(LSUWriteDataM)); - endianswap #(`LLEN) loadswap(.BigEndianM, .a(ReadDataWordMuxM), .y(LittleEndianReadDataWordM)); + endianswap #(`LLEN) loadswap(.BigEndianM, .a(ReadDataWordMuxSwapM), .y(LittleEndianReadDataWordM)); end else begin assign LSUWriteDataM = LittleEndianWriteDataM; assign LittleEndianReadDataWordM = ReadDataWordMuxM;