diff --git a/src/mmu/tlb/tlblru.sv b/src/mmu/tlb/tlblru.sv
index 6cdb475e..4cabb33a 100644
--- a/src/mmu/tlb/tlblru.sv
+++ b/src/mmu/tlb/tlblru.sv
@@ -50,7 +50,5 @@ module tlblru #(parameter TLB_ENTRIES = 8) (
   assign RUBitsAccessed = AccessLines | RUBits;
   assign AllUsed = &RUBitsAccessed; // if all recently used, then clear to none
   assign RUBitsNext = AllUsed ? 0 : RUBitsAccessed; 
-
-  // enable must be ORd with TLBFlush to ensure flop fires on a flush.  DH 7/8/21
-  flopenrc #(TLB_ENTRIES) lrustate(clk, reset, TLBFlush, (CAMHit | TLBWrite), RUBitsNext, RUBits);
+  flopenr #(TLB_ENTRIES) lrustate(clk, reset, (CAMHit | TLBWrite), RUBitsNext, RUBits);
 endmodule