From f6aafd6bad0575f59f71d3a0277d457aabd5e5cb Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 28 Jan 2023 17:56:56 -0600 Subject: [PATCH] Fixed bug with the new csr. --- pipelined/src/privileged/csrc.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/privileged/csrc.sv b/pipelined/src/privileged/csrc.sv index bd5ede79..94dbcaf4 100644 --- a/pipelined/src/privileged/csrc.sv +++ b/pipelined/src/privileged/csrc.sv @@ -97,7 +97,7 @@ module csrc #(parameter assign CounterEvent[12] = DCacheMiss; // data cache miss assign CounterEvent[13] = ICacheAccess; // instruction cache access assign CounterEvent[14] = ICacheMiss; // instruction cache miss - assign CounterEvent[15] = BPPredWrongM; // branch predictor wrong + assign CounterEvent[15] = BPPredWrongM & InstrValidNotFlushedM; // branch predictor wrong assign CounterEvent[`COUNTERS-1:16] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions end