diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test
index 84d04381..be67c99b 160000
--- a/addins/riscv-arch-test
+++ b/addins/riscv-arch-test
@@ -1 +1 @@
-Subproject commit 84d043817f75f752c9873326475e11f16e3a6f7c
+Subproject commit be67c99bd461742aa1c100bcc0732657faae2230
diff --git a/fpga/README.md b/fpga/README.md
new file mode 100644
index 00000000..eb08171a
--- /dev/null
+++ b/fpga/README.md
@@ -0,0 +1,46 @@
+The FPGA currently only targets the VCU118 board.
+
+* Build Process
+
+cd generator
+make 
+
+* Description
+
+The generator makefile creates 4 IP blocks; proc_sys_reset, ddr4,
+axi_clock_converter, and ahblite_axi_bridge.  Then it reads in the 4 IP blocks
+and builds wally.  fpga/src/fpgaTop.v is the top level which instanciates
+wallypipelinedsoc.sv and the 4 IP blocks.  The FPGA include and ILA (In logic
+analyzer) which provides the current instruction PCM, instrM, etc along with
+a large number of debuging signals.
+
+* Programming the flash card
+You'll need to write the linux image to the flash card.  Use the convert2bin.py 
+script in wally-pipelined/linux-testgen/linux-testvectors/ to convert the ram.txt
+file from QEMU's preload to generate the binary.  Then to copy
+ sudo dd if=ram.bin of=<path to flash card>.
+
+* Loading the FPGA
+
+After the build process is complete about 2 hrs on an i9-7900x. Launch vivado's
+gui and open the WallyFPGA.xpr project file.  Open the hardware manager under
+program and debug. Open target and then program with the bit file.
+
+* Test Run
+
+Once the FPGA is programed the 3 MSB LEDs in the upper right corner provide
+status of the reset and ddr4 calibration.  LED 7 should always be lit.
+LED 6 will light if the DDR4 is not calibrated.  LED 6 will be lit once
+wally begins running.
+
+Next the bootloader program will copy the flash card into the DDR4 memory.
+When this done the lower 5 LEDs will blink 5 times and then try to boot
+the program loaded in the DDR4 memory at physical address 0x8000_0000.
+
+* Connecting uart
+You'll need to connect both usb cables.  The first connects the FPGA programer
+while the connect connects UART.  UART is configured to use 57600 baud with 
+no parity, 8 data bits, and 1 stop bit.  sudo screen /dev/ttyUSB1 57600 should
+let you view the com port.
+
+
diff --git a/fpga/constraints/constraints.xdc b/fpga/constraints/constraints.xdc
index 9059dc7f..716136ec 100644
--- a/fpga/constraints/constraints.xdc
+++ b/fpga/constraints/constraints.xdc
@@ -282,7 +282,7 @@ set_property PACKAGE_PIN G22 [get_ports {c0_ddr4_dm_dbi_n[7]}]
 
 
 
-set_max_delay -datapath_only -from [get_pins wrapper_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins wrapper_i/proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000
+set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000
 
 
 set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n]
diff --git a/fpga/constraints/debug.xdc b/fpga/constraints/debug.xdc
index cd1b265d..9227ba6f 100644
--- a/fpga/constraints/debug.xdc
+++ b/fpga/constraints/debug.xdc
@@ -1,26 +1,17 @@
 ##### debugger #####
 
+connect_debug_port u_ila_0/probe34 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[3]}]]
+connect_debug_port u_ila_0/probe69 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/SDCCmdOE]]
+connect_debug_port u_ila_0/probe70 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/SDCCmdOut]]
 
-
-
-
-
-
-connect_debug_port u_ila_0/probe34 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[3]}]]
-connect_debug_port u_ila_0/probe69 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/SDCCmdOE]]
-connect_debug_port u_ila_0/probe70 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/SDCCmdOut]]
-
-
-
-
-connect_debug_port u_ila_0/probe17 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[64]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[65]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[66]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[67]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[68]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[69]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[70]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[71]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[72]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[73]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[74]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[75]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[76]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[77]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[78]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[79]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[80]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[81]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[82]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[83]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[84]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[85]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[86]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[87]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[88]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[89]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[90]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[91]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[92]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[93]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[94]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[95]}]]
-connect_debug_port u_ila_0/probe37 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/CountP1[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/CountP1[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/CountP1[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/CountP1[3]}]]
-connect_debug_port u_ila_0/probe46 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/NextCount[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/NextCount[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/NextCount[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/NextCount[3]}]]
-connect_debug_port u_ila_0/probe75 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_SD_RESTARTING]]
-connect_debug_port u_ila_0/probe82 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/w_bad_card]]
-connect_debug_port u_ila_0/probe83 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_BUSY_EN]]
-connect_debug_port u_ila_0/probe89 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/w_resend_last_command]]
-connect_debug_port u_ila_0/probe90 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_SD_CMD_RX]]
+connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[64]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[65]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[66]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[67]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[68]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[69]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[70]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[71]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[72]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[73]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[74]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[75]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[76]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[77]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[78]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[79]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[80]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[81]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[82]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[83]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[84]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[85]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[86]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[87]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[88]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[89]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[90]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[91]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[92]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[93]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[94]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[95]}]]
+connect_debug_port u_ila_0/probe37 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/CountP1[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/CountP1[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/CountP1[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/CountP1[3]}]]
+connect_debug_port u_ila_0/probe46 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/NextCount[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/NextCount[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/NextCount[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/NextCount[3]}]]
+connect_debug_port u_ila_0/probe75 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_SD_RESTARTING]]
+connect_debug_port u_ila_0/probe82 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/w_bad_card]]
+connect_debug_port u_ila_0/probe83 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_BUSY_EN]]
+connect_debug_port u_ila_0/probe89 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/w_resend_last_command]]
+connect_debug_port u_ila_0/probe90 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_SD_CMD_RX]]
 
 create_debug_core u_ila_0 ila
 set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
@@ -35,291 +26,291 @@ set_property port_width 1 [get_debug_ports u_ila_0/clk]
 connect_debug_port u_ila_0/clk [get_nets [list wrapper_i/ddr4_0/inst/u_ddr4_infrastructure/addn_ui_clkout1]]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
 set_property port_width 12 [get_debug_ports u_ila_0/probe0]
-connect_debug_port u_ila_0/probe0 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[11]}]]
+connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/hart/priv/trap/PendingIntsM[0]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[1]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[2]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[3]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[4]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[5]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[6]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[7]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[8]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[9]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[10]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[11]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
 set_property port_width 4 [get_debug_ports u_ila_0/probe1]
-connect_debug_port u_ila_0/probe1 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[3]}]]
+connect_debug_port u_ila_0/probe1 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[3]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
 set_property port_width 4 [get_debug_ports u_ila_0/probe2]
-connect_debug_port u_ila_0/probe2 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[3]}]]
+connect_debug_port u_ila_0/probe2 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[3]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
 set_property port_width 4 [get_debug_ports u_ila_0/probe3]
-connect_debug_port u_ila_0/probe3 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[3]}]]
+connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[3]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
 set_property port_width 6 [get_debug_ports u_ila_0/probe4]
-connect_debug_port u_ila_0/probe4 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[11]}]]
+connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[11]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
 set_property port_width 64 [get_debug_ports u_ila_0/probe5]
-connect_debug_port u_ila_0/probe5 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[63]}]]
+connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[0]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[2]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[4]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[6]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[8]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[10]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[11]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[12]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[13]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[14]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[15]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[16]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[17]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[18]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[19]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[20]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[21]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[22]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[23]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[24]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[25]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[26]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[27]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[28]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[29]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[30]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[31]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[32]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[33]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[34]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[35]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[36]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[37]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[38]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[39]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[40]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[41]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[42]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[43]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[44]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[45]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[46]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[47]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[48]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[49]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[50]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[51]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[52]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[53]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[54]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[55]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[56]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[57]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[58]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[59]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[60]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[61]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[62]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[63]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
 set_property port_width 64 [get_debug_ports u_ila_0/probe6]
-connect_debug_port u_ila_0/probe6 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[63]}]]
+connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[0]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[2]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[4]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[6]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[8]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[10]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[11]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[12]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[13]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[14]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[15]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[16]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[17]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[18]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[19]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[20]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[21]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[22]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[23]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[24]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[25]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[26]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[27]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[28]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[29]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[30]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[31]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[32]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[33]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[34]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[35]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[36]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[37]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[38]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[39]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[40]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[41]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[42]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[43]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[44]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[45]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[46]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[47]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[48]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[49]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[50]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[51]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[52]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[53]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[54]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[55]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[56]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[57]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[58]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[59]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[60]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[61]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[62]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[63]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
 set_property port_width 64 [get_debug_ports u_ila_0/probe7]
-connect_debug_port u_ila_0/probe7 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[63]}]]
+connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[0]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[2]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[4]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[6]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[8]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[10]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[11]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[12]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[13]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[14]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[15]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[16]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[17]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[18]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[19]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[20]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[21]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[22]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[23]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[24]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[25]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[26]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[27]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[28]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[29]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[30]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[31]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[32]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[33]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[34]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[35]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[36]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[37]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[38]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[39]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[40]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[41]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[42]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[43]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[44]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[45]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[46]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[47]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[48]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[49]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[50]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[51]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[52]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[53]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[54]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[55]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[56]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[57]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[58]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[59]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[60]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[61]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[62]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[63]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
 set_property port_width 6 [get_debug_ports u_ila_0/probe8]
-connect_debug_port u_ila_0/probe8 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[11]}]]
+connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[11]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
 set_property port_width 64 [get_debug_ports u_ila_0/probe9]
-connect_debug_port u_ila_0/probe9 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[63]}]]
+connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[0]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[2]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[4]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[6]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[8]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[10]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[11]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[12]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[13]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[14]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[15]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[16]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[17]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[18]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[19]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[20]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[21]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[22]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[23]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[24]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[25]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[26]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[27]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[28]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[29]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[30]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[31]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[32]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[33]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[34]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[35]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[36]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[37]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[38]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[39]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[40]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[41]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[42]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[43]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[44]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[45]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[46]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[47]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[48]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[49]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[50]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[51]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[52]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[53]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[54]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[55]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[56]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[57]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[58]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[59]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[60]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[61]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[62]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[63]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
 set_property port_width 6 [get_debug_ports u_ila_0/probe10]
-connect_debug_port u_ila_0/probe10 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIP_REGW[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIP_REGW[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIP_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIP_REGW[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIP_REGW[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIP_REGW[11]}]]
+connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsoc/hart/priv/trap/MIP_REGW[1]} {wallypipelinedsoc/hart/priv/trap/MIP_REGW[3]} {wallypipelinedsoc/hart/priv/trap/MIP_REGW[5]} {wallypipelinedsoc/hart/priv/trap/MIP_REGW[7]} {wallypipelinedsoc/hart/priv/trap/MIP_REGW[9]} {wallypipelinedsoc/hart/priv/trap/MIP_REGW[11]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
 set_property port_width 64 [get_debug_ports u_ila_0/probe11]
-connect_debug_port u_ila_0/probe11 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[63]}]]
+connect_debug_port u_ila_0/probe11 [get_nets [list {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[0]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[1]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[2]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[3]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[4]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[5]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[6]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[7]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[8]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[9]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[10]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[11]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[12]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[13]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[14]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[15]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[16]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[17]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[18]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[19]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[20]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[21]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[22]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[23]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[24]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[25]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[26]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[27]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[28]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[29]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[30]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[31]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[32]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[33]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[34]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[35]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[36]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[37]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[38]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[39]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[40]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[41]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[42]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[43]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[44]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[45]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[46]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[47]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[48]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[49]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[50]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[51]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[52]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[53]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[54]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[55]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[56]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[57]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[58]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[59]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[60]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[61]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[62]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[63]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
 set_property port_width 6 [get_debug_ports u_ila_0/probe12]
-connect_debug_port u_ila_0/probe12 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIE_REGW[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIE_REGW[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIE_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIE_REGW[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIE_REGW[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIE_REGW[11]}]]
+connect_debug_port u_ila_0/probe12 [get_nets [list {wallypipelinedsoc/hart/priv/trap/MIE_REGW[1]} {wallypipelinedsoc/hart/priv/trap/MIE_REGW[3]} {wallypipelinedsoc/hart/priv/trap/MIE_REGW[5]} {wallypipelinedsoc/hart/priv/trap/MIE_REGW[7]} {wallypipelinedsoc/hart/priv/trap/MIE_REGW[9]} {wallypipelinedsoc/hart/priv/trap/MIE_REGW[11]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
 set_property port_width 64 [get_debug_ports u_ila_0/probe13]
-connect_debug_port u_ila_0/probe13 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[63]}]]
+connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[0]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[1]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[2]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[3]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[4]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[5]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[6]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[7]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[8]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[9]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[10]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[11]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[12]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[13]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[14]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[15]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[16]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[17]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[18]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[19]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[20]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[21]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[22]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[23]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[24]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[25]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[26]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[27]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[28]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[29]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[30]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[31]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[32]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[33]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[34]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[35]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[36]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[37]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[38]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[39]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[40]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[41]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[42]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[43]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[44]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[45]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[46]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[47]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[48]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[49]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[50]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[51]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[52]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[53]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[54]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[55]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[56]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[57]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[58]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[59]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[60]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[61]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[62]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[63]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
 set_property port_width 3 [get_debug_ports u_ila_0/probe14]
-connect_debug_port u_ila_0/probe14 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SIP_REGW[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SIP_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SIP_REGW[9]}]]
+connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsoc/hart/priv/trap/SIP_REGW[1]} {wallypipelinedsoc/hart/priv/trap/SIP_REGW[5]} {wallypipelinedsoc/hart/priv/trap/SIP_REGW[9]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
 set_property port_width 63 [get_debug_ports u_ila_0/probe15]
-connect_debug_port u_ila_0/probe15 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[63]}]]
+connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[0]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[2]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[3]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[4]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[5]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[6]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[7]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[8]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[9]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[10]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[11]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[12]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[13]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[14]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[15]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[16]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[17]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[18]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[19]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[20]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[21]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[22]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[23]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[24]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[25]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[26]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[27]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[28]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[29]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[30]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[31]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[32]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[33]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[34]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[35]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[36]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[37]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[38]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[39]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[40]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[41]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[42]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[43]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[44]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[45]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[46]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[47]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[48]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[49]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[50]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[51]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[52]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[53]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[54]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[55]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[56]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[57]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[58]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[59]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[60]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[61]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[62]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[63]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
 set_property port_width 3 [get_debug_ports u_ila_0/probe16]
-connect_debug_port u_ila_0/probe16 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SIE_REGW[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SIE_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SIE_REGW[9]}]]
+connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/hart/priv/trap/SIE_REGW[1]} {wallypipelinedsoc/hart/priv/trap/SIE_REGW[5]} {wallypipelinedsoc/hart/priv/trap/SIE_REGW[9]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
 set_property port_width 64 [get_debug_ports u_ila_0/probe17]
-connect_debug_port u_ila_0/probe17 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[63]}]]
+connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/hart/ReadDataM[0]} {wallypipelinedsoc/hart/ReadDataM[1]} {wallypipelinedsoc/hart/ReadDataM[2]} {wallypipelinedsoc/hart/ReadDataM[3]} {wallypipelinedsoc/hart/ReadDataM[4]} {wallypipelinedsoc/hart/ReadDataM[5]} {wallypipelinedsoc/hart/ReadDataM[6]} {wallypipelinedsoc/hart/ReadDataM[7]} {wallypipelinedsoc/hart/ReadDataM[8]} {wallypipelinedsoc/hart/ReadDataM[9]} {wallypipelinedsoc/hart/ReadDataM[10]} {wallypipelinedsoc/hart/ReadDataM[11]} {wallypipelinedsoc/hart/ReadDataM[12]} {wallypipelinedsoc/hart/ReadDataM[13]} {wallypipelinedsoc/hart/ReadDataM[14]} {wallypipelinedsoc/hart/ReadDataM[15]} {wallypipelinedsoc/hart/ReadDataM[16]} {wallypipelinedsoc/hart/ReadDataM[17]} {wallypipelinedsoc/hart/ReadDataM[18]} {wallypipelinedsoc/hart/ReadDataM[19]} {wallypipelinedsoc/hart/ReadDataM[20]} {wallypipelinedsoc/hart/ReadDataM[21]} {wallypipelinedsoc/hart/ReadDataM[22]} {wallypipelinedsoc/hart/ReadDataM[23]} {wallypipelinedsoc/hart/ReadDataM[24]} {wallypipelinedsoc/hart/ReadDataM[25]} {wallypipelinedsoc/hart/ReadDataM[26]} {wallypipelinedsoc/hart/ReadDataM[27]} {wallypipelinedsoc/hart/ReadDataM[28]} {wallypipelinedsoc/hart/ReadDataM[29]} {wallypipelinedsoc/hart/ReadDataM[30]} {wallypipelinedsoc/hart/ReadDataM[31]} {wallypipelinedsoc/hart/ReadDataM[32]} {wallypipelinedsoc/hart/ReadDataM[33]} {wallypipelinedsoc/hart/ReadDataM[34]} {wallypipelinedsoc/hart/ReadDataM[35]} {wallypipelinedsoc/hart/ReadDataM[36]} {wallypipelinedsoc/hart/ReadDataM[37]} {wallypipelinedsoc/hart/ReadDataM[38]} {wallypipelinedsoc/hart/ReadDataM[39]} {wallypipelinedsoc/hart/ReadDataM[40]} {wallypipelinedsoc/hart/ReadDataM[41]} {wallypipelinedsoc/hart/ReadDataM[42]} {wallypipelinedsoc/hart/ReadDataM[43]} {wallypipelinedsoc/hart/ReadDataM[44]} {wallypipelinedsoc/hart/ReadDataM[45]} {wallypipelinedsoc/hart/ReadDataM[46]} {wallypipelinedsoc/hart/ReadDataM[47]} {wallypipelinedsoc/hart/ReadDataM[48]} {wallypipelinedsoc/hart/ReadDataM[49]} {wallypipelinedsoc/hart/ReadDataM[50]} {wallypipelinedsoc/hart/ReadDataM[51]} {wallypipelinedsoc/hart/ReadDataM[52]} {wallypipelinedsoc/hart/ReadDataM[53]} {wallypipelinedsoc/hart/ReadDataM[54]} {wallypipelinedsoc/hart/ReadDataM[55]} {wallypipelinedsoc/hart/ReadDataM[56]} {wallypipelinedsoc/hart/ReadDataM[57]} {wallypipelinedsoc/hart/ReadDataM[58]} {wallypipelinedsoc/hart/ReadDataM[59]} {wallypipelinedsoc/hart/ReadDataM[60]} {wallypipelinedsoc/hart/ReadDataM[61]} {wallypipelinedsoc/hart/ReadDataM[62]} {wallypipelinedsoc/hart/ReadDataM[63]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
 set_property port_width 64 [get_debug_ports u_ila_0/probe18]
-connect_debug_port u_ila_0/probe18 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[63]}]]
+connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsoc/hart/WriteDataM[0]} {wallypipelinedsoc/hart/WriteDataM[1]} {wallypipelinedsoc/hart/WriteDataM[2]} {wallypipelinedsoc/hart/WriteDataM[3]} {wallypipelinedsoc/hart/WriteDataM[4]} {wallypipelinedsoc/hart/WriteDataM[5]} {wallypipelinedsoc/hart/WriteDataM[6]} {wallypipelinedsoc/hart/WriteDataM[7]} {wallypipelinedsoc/hart/WriteDataM[8]} {wallypipelinedsoc/hart/WriteDataM[9]} {wallypipelinedsoc/hart/WriteDataM[10]} {wallypipelinedsoc/hart/WriteDataM[11]} {wallypipelinedsoc/hart/WriteDataM[12]} {wallypipelinedsoc/hart/WriteDataM[13]} {wallypipelinedsoc/hart/WriteDataM[14]} {wallypipelinedsoc/hart/WriteDataM[15]} {wallypipelinedsoc/hart/WriteDataM[16]} {wallypipelinedsoc/hart/WriteDataM[17]} {wallypipelinedsoc/hart/WriteDataM[18]} {wallypipelinedsoc/hart/WriteDataM[19]} {wallypipelinedsoc/hart/WriteDataM[20]} {wallypipelinedsoc/hart/WriteDataM[21]} {wallypipelinedsoc/hart/WriteDataM[22]} {wallypipelinedsoc/hart/WriteDataM[23]} {wallypipelinedsoc/hart/WriteDataM[24]} {wallypipelinedsoc/hart/WriteDataM[25]} {wallypipelinedsoc/hart/WriteDataM[26]} {wallypipelinedsoc/hart/WriteDataM[27]} {wallypipelinedsoc/hart/WriteDataM[28]} {wallypipelinedsoc/hart/WriteDataM[29]} {wallypipelinedsoc/hart/WriteDataM[30]} {wallypipelinedsoc/hart/WriteDataM[31]} {wallypipelinedsoc/hart/WriteDataM[32]} {wallypipelinedsoc/hart/WriteDataM[33]} {wallypipelinedsoc/hart/WriteDataM[34]} {wallypipelinedsoc/hart/WriteDataM[35]} {wallypipelinedsoc/hart/WriteDataM[36]} {wallypipelinedsoc/hart/WriteDataM[37]} {wallypipelinedsoc/hart/WriteDataM[38]} {wallypipelinedsoc/hart/WriteDataM[39]} {wallypipelinedsoc/hart/WriteDataM[40]} {wallypipelinedsoc/hart/WriteDataM[41]} {wallypipelinedsoc/hart/WriteDataM[42]} {wallypipelinedsoc/hart/WriteDataM[43]} {wallypipelinedsoc/hart/WriteDataM[44]} {wallypipelinedsoc/hart/WriteDataM[45]} {wallypipelinedsoc/hart/WriteDataM[46]} {wallypipelinedsoc/hart/WriteDataM[47]} {wallypipelinedsoc/hart/WriteDataM[48]} {wallypipelinedsoc/hart/WriteDataM[49]} {wallypipelinedsoc/hart/WriteDataM[50]} {wallypipelinedsoc/hart/WriteDataM[51]} {wallypipelinedsoc/hart/WriteDataM[52]} {wallypipelinedsoc/hart/WriteDataM[53]} {wallypipelinedsoc/hart/WriteDataM[54]} {wallypipelinedsoc/hart/WriteDataM[55]} {wallypipelinedsoc/hart/WriteDataM[56]} {wallypipelinedsoc/hart/WriteDataM[57]} {wallypipelinedsoc/hart/WriteDataM[58]} {wallypipelinedsoc/hart/WriteDataM[59]} {wallypipelinedsoc/hart/WriteDataM[60]} {wallypipelinedsoc/hart/WriteDataM[61]} {wallypipelinedsoc/hart/WriteDataM[62]} {wallypipelinedsoc/hart/WriteDataM[63]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
 set_property port_width 3 [get_debug_ports u_ila_0/probe19]
-connect_debug_port u_ila_0/probe19 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_ERROR_CODE_Q[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_ERROR_CODE_Q[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_ERROR_CODE_Q[2]}]]
+connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_ERROR_CODE_Q[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_ERROR_CODE_Q[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_ERROR_CODE_Q[2]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
 set_property port_width 5 [get_debug_ports u_ila_0/probe20]
-connect_debug_port u_ila_0/probe20 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[4]}]]
+connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[3]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[4]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
 set_property port_width 4 [get_debug_ports u_ila_0/probe21]
-connect_debug_port u_ila_0/probe21 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_IC_OUT[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_IC_OUT[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_IC_OUT[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_IC_OUT[3]}]]
+connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_IC_OUT[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_IC_OUT[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_IC_OUT[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_IC_OUT[3]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
 set_property port_width 4 [get_debug_ports u_ila_0/probe22]
-connect_debug_port u_ila_0/probe22 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[3]}]]
+connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[3]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
 set_property port_width 64 [get_debug_ports u_ila_0/probe23]
-connect_debug_port u_ila_0/probe23 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[63]}]]
+connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/hart/lsu/dcache/HWDATA[0]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[1]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[2]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[3]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[4]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[5]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[6]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[7]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[8]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[9]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[10]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[11]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[12]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[13]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[14]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[15]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[16]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[17]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[18]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[19]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[20]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[21]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[22]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[23]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[24]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[25]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[26]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[27]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[28]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[29]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[30]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[31]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[32]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[33]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[34]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[35]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[36]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[37]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[38]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[39]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[40]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[41]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[42]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[43]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[44]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[45]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[46]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[47]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[48]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[49]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[50]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[51]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[52]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[53]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[54]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[55]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[56]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[57]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[58]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[59]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[60]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[61]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[62]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[63]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
 set_property port_width 64 [get_debug_ports u_ila_0/probe24]
-connect_debug_port u_ila_0/probe24 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[63]}]]
+connect_debug_port u_ila_0/probe24 [get_nets [list {wallypipelinedsoc/hart/lsu/dcache/HRDATA[0]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[1]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[2]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[3]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[4]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[5]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[6]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[7]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[8]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[9]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[10]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[11]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[12]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[13]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[14]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[15]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[16]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[17]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[18]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[19]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[20]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[21]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[22]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[23]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[24]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[25]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[26]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[27]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[28]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[29]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[30]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[31]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[32]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[33]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[34]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[35]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[36]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[37]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[38]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[39]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[40]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[41]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[42]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[43]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[44]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[45]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[46]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[47]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[48]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[49]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[50]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[51]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[52]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[53]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[54]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[55]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[56]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[57]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[58]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[59]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[60]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[61]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[62]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[63]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
 set_property port_width 32 [get_debug_ports u_ila_0/probe25]
-connect_debug_port u_ila_0/probe25 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[31]}]]
+connect_debug_port u_ila_0/probe25 [get_nets [list {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[0]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[1]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[2]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[3]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[4]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[5]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[6]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[7]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[8]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[9]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[10]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[11]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[12]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[13]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[14]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[15]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[16]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[17]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[18]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[19]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[20]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[21]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[22]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[23]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[24]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[25]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[26]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[27]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[28]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[29]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[30]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[31]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
 set_property port_width 2 [get_debug_ports u_ila_0/probe26]
-connect_debug_port u_ila_0/probe26 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/DCtoAHBSizeM[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/DCtoAHBSizeM[1]}]]
+connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/hart/lsu/dcache/DCtoAHBSizeM[0]} {wallypipelinedsoc/hart/lsu/dcache/DCtoAHBSizeM[1]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
 set_property port_width 32 [get_debug_ports u_ila_0/probe27]
-connect_debug_port u_ila_0/probe27 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[31]}]]
+connect_debug_port u_ila_0/probe27 [get_nets [list {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[0]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[1]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[2]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[3]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[4]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[5]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[6]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[7]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[8]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[9]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[10]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[11]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[12]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[13]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[14]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[15]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[16]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[17]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[18]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[19]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[20]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[21]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[22]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[23]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[24]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[25]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[26]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[27]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[28]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[29]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[30]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[31]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
 set_property port_width 64 [get_debug_ports u_ila_0/probe28]
-connect_debug_port u_ila_0/probe28 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[63]}]]
+connect_debug_port u_ila_0/probe28 [get_nets [list {wallypipelinedsoc/hart/PCM[0]} {wallypipelinedsoc/hart/PCM[1]} {wallypipelinedsoc/hart/PCM[2]} {wallypipelinedsoc/hart/PCM[3]} {wallypipelinedsoc/hart/PCM[4]} {wallypipelinedsoc/hart/PCM[5]} {wallypipelinedsoc/hart/PCM[6]} {wallypipelinedsoc/hart/PCM[7]} {wallypipelinedsoc/hart/PCM[8]} {wallypipelinedsoc/hart/PCM[9]} {wallypipelinedsoc/hart/PCM[10]} {wallypipelinedsoc/hart/PCM[11]} {wallypipelinedsoc/hart/PCM[12]} {wallypipelinedsoc/hart/PCM[13]} {wallypipelinedsoc/hart/PCM[14]} {wallypipelinedsoc/hart/PCM[15]} {wallypipelinedsoc/hart/PCM[16]} {wallypipelinedsoc/hart/PCM[17]} {wallypipelinedsoc/hart/PCM[18]} {wallypipelinedsoc/hart/PCM[19]} {wallypipelinedsoc/hart/PCM[20]} {wallypipelinedsoc/hart/PCM[21]} {wallypipelinedsoc/hart/PCM[22]} {wallypipelinedsoc/hart/PCM[23]} {wallypipelinedsoc/hart/PCM[24]} {wallypipelinedsoc/hart/PCM[25]} {wallypipelinedsoc/hart/PCM[26]} {wallypipelinedsoc/hart/PCM[27]} {wallypipelinedsoc/hart/PCM[28]} {wallypipelinedsoc/hart/PCM[29]} {wallypipelinedsoc/hart/PCM[30]} {wallypipelinedsoc/hart/PCM[31]} {wallypipelinedsoc/hart/PCM[32]} {wallypipelinedsoc/hart/PCM[33]} {wallypipelinedsoc/hart/PCM[34]} {wallypipelinedsoc/hart/PCM[35]} {wallypipelinedsoc/hart/PCM[36]} {wallypipelinedsoc/hart/PCM[37]} {wallypipelinedsoc/hart/PCM[38]} {wallypipelinedsoc/hart/PCM[39]} {wallypipelinedsoc/hart/PCM[40]} {wallypipelinedsoc/hart/PCM[41]} {wallypipelinedsoc/hart/PCM[42]} {wallypipelinedsoc/hart/PCM[43]} {wallypipelinedsoc/hart/PCM[44]} {wallypipelinedsoc/hart/PCM[45]} {wallypipelinedsoc/hart/PCM[46]} {wallypipelinedsoc/hart/PCM[47]} {wallypipelinedsoc/hart/PCM[48]} {wallypipelinedsoc/hart/PCM[49]} {wallypipelinedsoc/hart/PCM[50]} {wallypipelinedsoc/hart/PCM[51]} {wallypipelinedsoc/hart/PCM[52]} {wallypipelinedsoc/hart/PCM[53]} {wallypipelinedsoc/hart/PCM[54]} {wallypipelinedsoc/hart/PCM[55]} {wallypipelinedsoc/hart/PCM[56]} {wallypipelinedsoc/hart/PCM[57]} {wallypipelinedsoc/hart/PCM[58]} {wallypipelinedsoc/hart/PCM[59]} {wallypipelinedsoc/hart/PCM[60]} {wallypipelinedsoc/hart/PCM[61]} {wallypipelinedsoc/hart/PCM[62]} {wallypipelinedsoc/hart/PCM[63]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
 set_property port_width 64 [get_debug_ports u_ila_0/probe29]
-connect_debug_port u_ila_0/probe29 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[63]}]]
+connect_debug_port u_ila_0/probe29 [get_nets [list {wallypipelinedsoc/hart/MemAdrM[0]} {wallypipelinedsoc/hart/MemAdrM[1]} {wallypipelinedsoc/hart/MemAdrM[2]} {wallypipelinedsoc/hart/MemAdrM[3]} {wallypipelinedsoc/hart/MemAdrM[4]} {wallypipelinedsoc/hart/MemAdrM[5]} {wallypipelinedsoc/hart/MemAdrM[6]} {wallypipelinedsoc/hart/MemAdrM[7]} {wallypipelinedsoc/hart/MemAdrM[8]} {wallypipelinedsoc/hart/MemAdrM[9]} {wallypipelinedsoc/hart/MemAdrM[10]} {wallypipelinedsoc/hart/MemAdrM[11]} {wallypipelinedsoc/hart/MemAdrM[12]} {wallypipelinedsoc/hart/MemAdrM[13]} {wallypipelinedsoc/hart/MemAdrM[14]} {wallypipelinedsoc/hart/MemAdrM[15]} {wallypipelinedsoc/hart/MemAdrM[16]} {wallypipelinedsoc/hart/MemAdrM[17]} {wallypipelinedsoc/hart/MemAdrM[18]} {wallypipelinedsoc/hart/MemAdrM[19]} {wallypipelinedsoc/hart/MemAdrM[20]} {wallypipelinedsoc/hart/MemAdrM[21]} {wallypipelinedsoc/hart/MemAdrM[22]} {wallypipelinedsoc/hart/MemAdrM[23]} {wallypipelinedsoc/hart/MemAdrM[24]} {wallypipelinedsoc/hart/MemAdrM[25]} {wallypipelinedsoc/hart/MemAdrM[26]} {wallypipelinedsoc/hart/MemAdrM[27]} {wallypipelinedsoc/hart/MemAdrM[28]} {wallypipelinedsoc/hart/MemAdrM[29]} {wallypipelinedsoc/hart/MemAdrM[30]} {wallypipelinedsoc/hart/MemAdrM[31]} {wallypipelinedsoc/hart/MemAdrM[32]} {wallypipelinedsoc/hart/MemAdrM[33]} {wallypipelinedsoc/hart/MemAdrM[34]} {wallypipelinedsoc/hart/MemAdrM[35]} {wallypipelinedsoc/hart/MemAdrM[36]} {wallypipelinedsoc/hart/MemAdrM[37]} {wallypipelinedsoc/hart/MemAdrM[38]} {wallypipelinedsoc/hart/MemAdrM[39]} {wallypipelinedsoc/hart/MemAdrM[40]} {wallypipelinedsoc/hart/MemAdrM[41]} {wallypipelinedsoc/hart/MemAdrM[42]} {wallypipelinedsoc/hart/MemAdrM[43]} {wallypipelinedsoc/hart/MemAdrM[44]} {wallypipelinedsoc/hart/MemAdrM[45]} {wallypipelinedsoc/hart/MemAdrM[46]} {wallypipelinedsoc/hart/MemAdrM[47]} {wallypipelinedsoc/hart/MemAdrM[48]} {wallypipelinedsoc/hart/MemAdrM[49]} {wallypipelinedsoc/hart/MemAdrM[50]} {wallypipelinedsoc/hart/MemAdrM[51]} {wallypipelinedsoc/hart/MemAdrM[52]} {wallypipelinedsoc/hart/MemAdrM[53]} {wallypipelinedsoc/hart/MemAdrM[54]} {wallypipelinedsoc/hart/MemAdrM[55]} {wallypipelinedsoc/hart/MemAdrM[56]} {wallypipelinedsoc/hart/MemAdrM[57]} {wallypipelinedsoc/hart/MemAdrM[58]} {wallypipelinedsoc/hart/MemAdrM[59]} {wallypipelinedsoc/hart/MemAdrM[60]} {wallypipelinedsoc/hart/MemAdrM[61]} {wallypipelinedsoc/hart/MemAdrM[62]} {wallypipelinedsoc/hart/MemAdrM[63]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
 set_property port_width 2 [get_debug_ports u_ila_0/probe30]
-connect_debug_port u_ila_0/probe30 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemRWM[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemRWM[1]}]]
+connect_debug_port u_ila_0/probe30 [get_nets [list {wallypipelinedsoc/hart/MemRWM[0]} {wallypipelinedsoc/hart/MemRWM[1]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
 set_property port_width 32 [get_debug_ports u_ila_0/probe31]
-connect_debug_port u_ila_0/probe31 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[31]}]]
+connect_debug_port u_ila_0/probe31 [get_nets [list {wallypipelinedsoc/hart/InstrM[0]} {wallypipelinedsoc/hart/InstrM[1]} {wallypipelinedsoc/hart/InstrM[2]} {wallypipelinedsoc/hart/InstrM[3]} {wallypipelinedsoc/hart/InstrM[4]} {wallypipelinedsoc/hart/InstrM[5]} {wallypipelinedsoc/hart/InstrM[6]} {wallypipelinedsoc/hart/InstrM[7]} {wallypipelinedsoc/hart/InstrM[8]} {wallypipelinedsoc/hart/InstrM[9]} {wallypipelinedsoc/hart/InstrM[10]} {wallypipelinedsoc/hart/InstrM[11]} {wallypipelinedsoc/hart/InstrM[12]} {wallypipelinedsoc/hart/InstrM[13]} {wallypipelinedsoc/hart/InstrM[14]} {wallypipelinedsoc/hart/InstrM[15]} {wallypipelinedsoc/hart/InstrM[16]} {wallypipelinedsoc/hart/InstrM[17]} {wallypipelinedsoc/hart/InstrM[18]} {wallypipelinedsoc/hart/InstrM[19]} {wallypipelinedsoc/hart/InstrM[20]} {wallypipelinedsoc/hart/InstrM[21]} {wallypipelinedsoc/hart/InstrM[22]} {wallypipelinedsoc/hart/InstrM[23]} {wallypipelinedsoc/hart/InstrM[24]} {wallypipelinedsoc/hart/InstrM[25]} {wallypipelinedsoc/hart/InstrM[26]} {wallypipelinedsoc/hart/InstrM[27]} {wallypipelinedsoc/hart/InstrM[28]} {wallypipelinedsoc/hart/InstrM[29]} {wallypipelinedsoc/hart/InstrM[30]} {wallypipelinedsoc/hart/InstrM[31]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
 set_property port_width 1 [get_debug_ports u_ila_0/probe32]
-connect_debug_port u_ila_0/probe32 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBAck]]
+connect_debug_port u_ila_0/probe32 [get_nets [list wallypipelinedsoc/hart/lsu/dcache/AHBAck]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
 set_property port_width 1 [get_debug_ports u_ila_0/probe33]
-connect_debug_port u_ila_0/probe33 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBRead]]
+connect_debug_port u_ila_0/probe33 [get_nets [list wallypipelinedsoc/hart/lsu/dcache/AHBRead]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
 set_property port_width 1 [get_debug_ports u_ila_0/probe34]
-connect_debug_port u_ila_0/probe34 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBWrite]]
+connect_debug_port u_ila_0/probe34 [get_nets [list wallypipelinedsoc/hart/lsu/dcache/AHBWrite]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
 set_property port_width 1 [get_debug_ports u_ila_0/probe35]
-connect_debug_port u_ila_0/probe35 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/BreakpointFaultM]]
+connect_debug_port u_ila_0/probe35 [get_nets [list wallypipelinedsoc/hart/priv/trap/BreakpointFaultM]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
 set_property port_width 1 [get_debug_ports u_ila_0/probe36]
-connect_debug_port u_ila_0/probe36 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/EcallFaultM]]
+connect_debug_port u_ila_0/probe36 [get_nets [list wallypipelinedsoc/hart/priv/trap/EcallFaultM]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
 set_property port_width 1 [get_debug_ports u_ila_0/probe37]
-connect_debug_port u_ila_0/probe37 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/i_DAT0_Q]]
+connect_debug_port u_ila_0/probe37 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/i_DAT0_Q]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
 set_property port_width 1 [get_debug_ports u_ila_0/probe38]
-connect_debug_port u_ila_0/probe38 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/i_DATA_CRC16_GOOD]]
+connect_debug_port u_ila_0/probe38 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/i_DATA_CRC16_GOOD]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
 set_property port_width 1 [get_debug_ports u_ila_0/probe39]
-connect_debug_port u_ila_0/probe39 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/i_ERROR_CRC16]]
+connect_debug_port u_ila_0/probe39 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/i_ERROR_CRC16]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
 set_property port_width 1 [get_debug_ports u_ila_0/probe40]
-connect_debug_port u_ila_0/probe40 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/i_ERROR_DAT_TIMES_OUT]]
+connect_debug_port u_ila_0/probe40 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/i_ERROR_DAT_TIMES_OUT]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
 set_property port_width 1 [get_debug_ports u_ila_0/probe41]
-connect_debug_port u_ila_0/probe41 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/IllegalInstrFaultM]]
+connect_debug_port u_ila_0/probe41 [get_nets [list wallypipelinedsoc/hart/priv/trap/IllegalInstrFaultM]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
 set_property port_width 1 [get_debug_ports u_ila_0/probe42]
-connect_debug_port u_ila_0/probe42 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/InstrAccessFaultM]]
+connect_debug_port u_ila_0/probe42 [get_nets [list wallypipelinedsoc/hart/priv/trap/InstrAccessFaultM]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
 set_property port_width 1 [get_debug_ports u_ila_0/probe43]
-connect_debug_port u_ila_0/probe43 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/InstrPageFaultM]]
+connect_debug_port u_ila_0/probe43 [get_nets [list wallypipelinedsoc/hart/priv/trap/InstrPageFaultM]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
 set_property port_width 1 [get_debug_ports u_ila_0/probe44]
-connect_debug_port u_ila_0/probe44 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrValidM]]
+connect_debug_port u_ila_0/probe44 [get_nets [list wallypipelinedsoc/hart/InstrValidM]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
 set_property port_width 1 [get_debug_ports u_ila_0/probe45]
-connect_debug_port u_ila_0/probe45 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/LoadAccessFaultM]]
+connect_debug_port u_ila_0/probe45 [get_nets [list wallypipelinedsoc/hart/priv/trap/LoadAccessFaultM]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
 set_property port_width 1 [get_debug_ports u_ila_0/probe46]
-connect_debug_port u_ila_0/probe46 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/LoadMisalignedFaultM]]
+connect_debug_port u_ila_0/probe46 [get_nets [list wallypipelinedsoc/hart/priv/trap/LoadMisalignedFaultM]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
 set_property port_width 1 [get_debug_ports u_ila_0/probe47]
-connect_debug_port u_ila_0/probe47 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/LoadPageFaultM]]
+connect_debug_port u_ila_0/probe47 [get_nets [list wallypipelinedsoc/hart/priv/trap/LoadPageFaultM]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48]
 set_property port_width 1 [get_debug_ports u_ila_0/probe48]
-connect_debug_port u_ila_0/probe48 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/mretM]]
+connect_debug_port u_ila_0/probe48 [get_nets [list wallypipelinedsoc/hart/priv/trap/mretM]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49]
 set_property port_width 1 [get_debug_ports u_ila_0/probe49]
-connect_debug_port u_ila_0/probe49 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/o_G_CLK_SD_EN]]
+connect_debug_port u_ila_0/probe49 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/o_G_CLK_SD_EN]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50]
 set_property port_width 1 [get_debug_ports u_ila_0/probe50]
-connect_debug_port u_ila_0/probe50 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/o_SD_CLK]]
+connect_debug_port u_ila_0/probe50 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/o_SD_CLK]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51]
 set_property port_width 1 [get_debug_ports u_ila_0/probe51]
-connect_debug_port u_ila_0/probe51 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/o_SD_CMD]]
+connect_debug_port u_ila_0/probe51 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/o_SD_CMD]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52]
 set_property port_width 1 [get_debug_ports u_ila_0/probe52]
-connect_debug_port u_ila_0/probe52 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/o_SD_CMD_OE]]
+connect_debug_port u_ila_0/probe52 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/o_SD_CMD_OE]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53]
 set_property port_width 1 [get_debug_ports u_ila_0/probe53]
-connect_debug_port u_ila_0/probe53 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_SD_CMD_OE]]
+connect_debug_port u_ila_0/probe53 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_SD_CMD_OE]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54]
 set_property port_width 1 [get_debug_ports u_ila_0/probe54]
-connect_debug_port u_ila_0/probe54 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_ERROR_Q]]
+connect_debug_port u_ila_0/probe54 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_ERROR_Q]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55]
 set_property port_width 1 [get_debug_ports u_ila_0/probe55]
-connect_debug_port u_ila_0/probe55 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/sretM]]
+connect_debug_port u_ila_0/probe55 [get_nets [list wallypipelinedsoc/hart/priv/trap/sretM]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56]
 set_property port_width 1 [get_debug_ports u_ila_0/probe56]
-connect_debug_port u_ila_0/probe56 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/StoreAccessFaultM]]
+connect_debug_port u_ila_0/probe56 [get_nets [list wallypipelinedsoc/hart/priv/trap/StoreAccessFaultM]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57]
 set_property port_width 1 [get_debug_ports u_ila_0/probe57]
-connect_debug_port u_ila_0/probe57 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/StoreMisalignedFaultM]]
+connect_debug_port u_ila_0/probe57 [get_nets [list wallypipelinedsoc/hart/priv/trap/StoreMisalignedFaultM]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58]
 set_property port_width 1 [get_debug_ports u_ila_0/probe58]
-connect_debug_port u_ila_0/probe58 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/StorePageFaultM]]
+connect_debug_port u_ila_0/probe58 [get_nets [list wallypipelinedsoc/hart/priv/trap/StorePageFaultM]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59]
 set_property port_width 1 [get_debug_ports u_ila_0/probe59]
-connect_debug_port u_ila_0/probe59 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/TrapM]]
+connect_debug_port u_ila_0/probe59 [get_nets [list wallypipelinedsoc/hart/TrapM]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60]
 set_property port_width 1 [get_debug_ports u_ila_0/probe60]
-connect_debug_port u_ila_0/probe60 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_IC_EN]]
+connect_debug_port u_ila_0/probe60 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_IC_EN]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61]
 set_property port_width 1 [get_debug_ports u_ila_0/probe61]
-connect_debug_port u_ila_0/probe61 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_IC_RST]]
+connect_debug_port u_ila_0/probe61 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_IC_RST]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe62]
 set_property port_width 1 [get_debug_ports u_ila_0/probe62]
-connect_debug_port u_ila_0/probe62 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_IC_UP_DOWN]]
+connect_debug_port u_ila_0/probe62 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_IC_UP_DOWN]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe63]
 set_property port_width 1 [get_debug_ports u_ila_0/probe63]
-connect_debug_port u_ila_0/probe63 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/uart.uart/DTRb]]
+connect_debug_port u_ila_0/probe63 [get_nets [list wallypipelinedsoc/uncore/uart.uart/DTRb]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe64]
 set_property port_width 1 [get_debug_ports u_ila_0/probe64]
-connect_debug_port u_ila_0/probe64 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/uart.uart/INTR]]
+connect_debug_port u_ila_0/probe64 [get_nets [list wallypipelinedsoc/uncore/uart.uart/INTR]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe65]
 set_property port_width 1 [get_debug_ports u_ila_0/probe65]
-connect_debug_port u_ila_0/probe65 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/uart.uart/OUT1b]]
+connect_debug_port u_ila_0/probe65 [get_nets [list wallypipelinedsoc/uncore/uart.uart/OUT1b]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe66]
 set_property port_width 1 [get_debug_ports u_ila_0/probe66]
-connect_debug_port u_ila_0/probe66 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/uart.uart/OUT2b]]
+connect_debug_port u_ila_0/probe66 [get_nets [list wallypipelinedsoc/uncore/uart.uart/OUT2b]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe67]
 set_property port_width 1 [get_debug_ports u_ila_0/probe67]
-connect_debug_port u_ila_0/probe67 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/uart.uart/RTSb]]
+connect_debug_port u_ila_0/probe67 [get_nets [list wallypipelinedsoc/uncore/uart.uart/RTSb]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe68]
 set_property port_width 1 [get_debug_ports u_ila_0/probe68]
-connect_debug_port u_ila_0/probe68 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/uart.uart/RXRDYb]]
+connect_debug_port u_ila_0/probe68 [get_nets [list wallypipelinedsoc/uncore/uart.uart/RXRDYb]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe69]
 set_property port_width 1 [get_debug_ports u_ila_0/probe69]
-connect_debug_port u_ila_0/probe69 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/uart.uart/SIN]]
+connect_debug_port u_ila_0/probe69 [get_nets [list wallypipelinedsoc/uncore/uart.uart/SIN]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe70]
 set_property port_width 1 [get_debug_ports u_ila_0/probe70]
-connect_debug_port u_ila_0/probe70 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/uart.uart/SOUT]]
+connect_debug_port u_ila_0/probe70 [get_nets [list wallypipelinedsoc/uncore/uart.uart/SOUT]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe71]
 set_property port_width 1 [get_debug_ports u_ila_0/probe71]
-connect_debug_port u_ila_0/probe71 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/uart.uart/TXRDYb]]
+connect_debug_port u_ila_0/probe71 [get_nets [list wallypipelinedsoc/uncore/uart.uart/TXRDYb]]
 set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
 set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
 set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl
index affeb45b..b9f55c0e 100644
--- a/fpga/generator/wally.tcl
+++ b/fpga/generator/wally.tcl
@@ -20,68 +20,86 @@ read_verilog  {../src/fpgaTop.v}
 set_property include_dirs {../../wally-pipelined/config/fpga ../../wally-pipelined/config/shared} [current_fileset]
 
 # contrainsts generated by the IP blocks
-add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_0/bd_1ba7_microblaze_I_0.xdc
-set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_0/bd_1ba7_microblaze_I_0.xdc]
 
-add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0_board.xdc
-set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0_board.xdc]
+#add_files -fileset constrs_1 -norecurse IP/xlnx_ahblite_axi_bridge.gen/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge_ooc.xdc
+#set_property PROCESSING_ORDER EARLY [get_files  IP/xlnx_ahblite_axi_bridge.gen/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge_ooc.xdc]
 
-add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0.xdc
-set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0.xdc]
+#add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_ooc.xdc
+#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_ooc.xdc]
 
-add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_2/bd_1ba7_ilmb_0.xdc
-set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_2/bd_1ba7_ilmb_0.xdc]
+#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_1/par/xlnx_ddr4_phy_ooc.xdc
+#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_1/par/xlnx_ddr4_phy_ooc.xdc]
 
-add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_3/bd_1ba7_dlmb_0.xdc
-set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_3/bd_1ba7_dlmb_0.xdc]
+#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_0/bd_1ba7_microblaze_I_0.xdc
+#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_0/bd_1ba7_microblaze_I_0.xdc]
 
-add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_10/bd_1ba7_iomodule_0_0_board.xdc
-set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_10/bd_1ba7_iomodule_0_0_board.xdc]
+#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0_board.xdc
+#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0_board.xdc]
 
-add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_board.xdc
-set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_board.xdc]
+#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_2/bd_1ba7_ilmb_0.xdc
+#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_2/bd_1ba7_ilmb_0.xdc]
+
+#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_3/bd_1ba7_dlmb_0.xdc
+#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_3/bd_1ba7_dlmb_0.xdc]
+
+#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0.xdc
+#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0.xdc]
+
+#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_6/bd_1ba7_lmb_bram_I_0_ooc.xdc
+#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_6/bd_1ba7_lmb_bram_I_0_ooc.xdc]
+
+#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_9/bd_1ba7_second_lmb_bram_I_0_ooc.xdc
+#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_9/bd_1ba7_second_lmb_bram_I_0_ooc.xdc]
+
+#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_10/bd_1ba7_iomodule_0_0_board.xdc
+#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_10/bd_1ba7_iomodule_0_0_board.xdc]
+
+#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/bd_1ba7_ooc.xdc
+#set_property PROCESSING_ORDER EARLY [get_files  IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/bd_1ba7_ooc.xdc]
+
+#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_board.xdc
+#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_board.xdc]
+
+#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_ooc.xdc
+#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_ooc.xdc]
+
+#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/xlnx_ddr4_board.xdc
+#set_property PROCESSING_ORDER LATE [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/xlnx_ddr4_board.xdc]
+
+#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/par/xlnx_ddr4.xdc
+#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/par/xlnx_ddr4.xdc]
+
+#add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_board.xdc
+#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_board.xdc]
+
+#add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xdc
+#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xdc]
+
+#add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_ooc.xdc
+#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_ooc.xdc]
 
-add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_board.xdc
-set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_board.xdc]
 
-add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xdc
-set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xdc]
 
 add_files -fileset constrs_1 -norecurse ../constraints/constraints.xdc
 set_property PROCESSING_ORDER NORMAL [get_files  ../constraints/constraints.xdc]
 
-add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_clocks.xdc
-set_property PROCESSING_ORDER LATE [get_files IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_clocks.xdc]
-
-add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/xlnx_ddr4_board.xdc
-set_property PROCESSING_ORDER LATE [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/xlnx_ddr4_board.xdc]
-
-add_files -fileset constrs_1 -norecurse IP/xlnx_ahblite_axi_bridge.gen/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge_ooc.xdc
-set_property PROCESSING_ORDER EARLY [get_files  IP/xlnx_ahblite_axi_bridge.gen/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge_ooc.xdc]
-
-
-add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/par/xlnx_ddr4.xdc
-set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/par/xlnx_ddr4.xdc]
-
-
-add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_1/par/xlnx_ddr4_phy_ooc.xdc
+# implementation only
+#add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_clocks.xdc
+#set_property PROCESSING_ORDER LATE [get_files IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_clocks.xdc]
+
+
+
+
 
 
 
-add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_ooc.xdc
-
-add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_ooc.xdc
 
 
-add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_ooc.xdc
 
 
 
 #add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_0/bd_1ba7_microblaze_I_0_ooc_debug.xdc
-#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_9/bd_1ba7_second_lmb_bram_I_0_ooc.xdc
-#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_6/bd_1ba7_lmb_bram_I_0_ooc.xdc
-#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/bd_1ba7_ooc.xdc
-#add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_ooc.xdc
+
 #add_files -fileset constrs_1 -norecurse IP/xlnx_ahblite_axi_bridge.runs/xlnx_ahblite_axi_bridge_synth_1/dont_touch.xdc
 
 #add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.runs/xlnx_proc_sys_reset_synth_1/dont_touch.xdc
@@ -98,14 +116,13 @@ add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/
 # define top level
 set_property top fpgaTop [current_fileset]
 
-set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_ooc.xdc]
-set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_1/par/xlnx_ddr4_phy_ooc.xdc]
-set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_ooc.xdc]
-set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_ooc.xdc]
+#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_ooc.xdc]
+#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_ooc.xdc]
 
 
 update_compile_order -fileset sources_1
-update_compile_order -fileset constrs_1
+# this line is wrong vvv
+#update_compile_order -fileset constrs_1
 # This is important as the ddr4 IP contains the generate clock constraint which the user constraints depend on.
 report_compile_order -constraints > reports/compile_order.rpt
 
@@ -130,6 +147,8 @@ report_utilization -hierarchical                                        -file re
 report_cdc                                                              -file reports/cdc.rpt
 report_clock_interaction                                                -file reports/clock_interaction.rpt
 
+source ../constraints/debug2.xdc
+
 
 # set for RuntimeOptimized implementation
 #set_property "steps.place_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v
index d9751c9c..d299e551 100644
--- a/fpga/src/fpgaTop.v
+++ b/fpga/src/fpgaTop.v
@@ -192,8 +192,8 @@ module fpgaTop
   
   // SD Card Tristate
   IOBUF iobufSDCMD(.T(~SDCCmdOE), // iobuf's T is active low
-		   .I(SDCCmdIn),
-		   .O(SDCCmdOut),
+		   .I(SDCCmdOut),
+		   .O(SDCCmdIn),
 		   .IO(SDCCmd));
 
   // reset controller XILINX IP
diff --git a/wally-pipelined/fpu-testfloat/FMA/tbgen/tb.sv b/wally-pipelined/fpu-testfloat/FMA/tbgen/tb.sv
index de5e849d..7d984dff 100644
--- a/wally-pipelined/fpu-testfloat/FMA/tbgen/tb.sv
+++ b/wally-pipelined/fpu-testfloat/FMA/tbgen/tb.sv
@@ -1,5 +1,10 @@
 
-`include "../../../config/rv64icfd/wally-config.vh"
+//`include "../../../config/old/rv64icfd/wally-config.vh"
+
+`define FLEN 64//(`Q_SUPPORTED ? 128 : `D_SUPPORTED ? 64 : 32)
+`define NE   11//(`Q_SUPPORTED ? 15 : `D_SUPPORTED ? 11 : 8)
+`define NF   52//(`Q_SUPPORTED ? 112 : `D_SUPPORTED ? 52 : 23)
+`define XLEN 64
 module testbench3();
 
  logic [31:0] errors=0;
@@ -174,8 +179,9 @@ always @(posedge clk)
  // check results on falling edge of clk
   always @(negedge clk) begin
  
-  //  fp = $fopen("/home/kparry/riscv-wally/wally-pipelined/src/fpu/FMA/tbgen/results.dat","w");
 	if((FmtE==1'b1) & (FMAFlgM != flags[4:0] || (!wnan && (FMAResM != ans)) || (wnan && ansnan && ~((XNaNE && (FMAResM[`FLEN-2:0] == {XExpE,1'b1,X[`NF-2:0]})) || (YNaNE && (FMAResM[`FLEN-2:0] == {YExpE,1'b1,Y[`NF-2:0]}))  || (ZNaNE && (FMAResM[`FLEN-2:0] == {ZExpE,1'b1,Z[`NF-2:0]})) || (FMAResM[`FLEN-2:0] == ans[`FLEN-2:0]))))) begin
+  //  fp = $fopen("/home/kparry/riscv-wally/wally-pipelined/src/fpu/FMA/tbgen/results.dat","w");
+	// if((FmtE==1'b1) & (FMAFlgM != flags[4:0] || (FMAResM != ans))) begin
         $display( "%h %h %h %h %h %h %h  Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags);
 		if(FMAResM == 64'h8000000000000000) $display( "FMAResM=-zero ");
 		if(XDenormE) $display( "xdenorm ");
@@ -193,7 +199,7 @@ always @(posedge clk)
 		if(ans[`FLEN-2:`NF] == {`NE{1'b1}} && ans[`NF-1:0] != 0 && ~ans[`NF-1]) $display( "ans=sigNaN ");
 		if(ans[`FLEN-2:`NF] == {`NE{1'b1}} && ans[`NF-1:0] != 0 && ans[`NF-1]) $display( "ans=qutNaN ");
         errors = errors + 1;
-
+	  //if (errors == 10)
 		$stop;
     end
     if((FmtE==1'b0)&(FMAFlgM != flags[4:0] || (!wnan && (FMAResM != ans)) || (wnan && ansnan && ~(((XNaNE && (FMAResM[30:0] == {X[30:23],1'b1,X[21:0]})) || (YNaNE && (FMAResM[30:0] == {Y[30:23],1'b1,Y[21:0]}))  || (ZNaNE && (FMAResM[30:0] == {Z[30:23],1'b1,Z[21:0]})) || (FMAResM[30:0] == ans[30:0]))) ))) begin
diff --git a/wally-pipelined/linux-testgen/linux-testvectors/convert2bin.py b/wally-pipelined/linux-testgen/linux-testvectors/convert2bin.py
new file mode 100755
index 00000000..78349a5d
--- /dev/null
+++ b/wally-pipelined/linux-testgen/linux-testvectors/convert2bin.py
@@ -0,0 +1,13 @@
+#!/usr/bin/python3
+
+asciiBinFile = 'ram.txt'
+binFile = 'ram.bin'
+
+asciiBinFP = open(asciiBinFile, 'r')
+binFP = open (binFile, 'wb')
+
+for line in asciiBinFP.readlines():
+    binFP.write(int(line, 16).to_bytes(8, byteorder='little', signed=False))
+
+asciiBinFP.close()
+binFP.close()    
diff --git a/wally-pipelined/regression/make-tests.sh b/wally-pipelined/regression/make-tests.sh
index e64f9445..dfc7d618 100755
--- a/wally-pipelined/regression/make-tests.sh
+++ b/wally-pipelined/regression/make-tests.sh
@@ -9,4 +9,6 @@ make allclean
 make
 make XLEN=32
 exe2memfile.pl work/*/*/*.elf
-cd ../../wally-pipelined/regression
+cd ../linux-testgen/linux-testvectors
+./tvLinker.sh
+cd ../../../wally-pipelined/regression
diff --git a/wally-pipelined/regression/regression-wally.py b/wally-pipelined/regression/regression-wally.py
index 810e7ca9..828c2b7c 100755
--- a/wally-pipelined/regression/regression-wally.py
+++ b/wally-pipelined/regression/regression-wally.py
@@ -10,9 +10,11 @@
 # output.
 #
 ##################################
-import sys
+import sys,os
 
 from collections import namedtuple
+regressionDir = os.path.dirname(os.path.abspath(__file__))
+os.chdir(regressionDir)
 TestCase = namedtuple("TestCase", ['name', 'cmd', 'grepstr'])
 # name:     the name of this test configuration (used in printing human-readable
 #           output and picking logfile names)
@@ -78,6 +80,7 @@ def run_test_case(config):
     logname = "logs/wally_"+config.name+".log"
     cmd = config.cmd.format(logname)
     print(cmd)
+    os.chdir(regressionDir)
     os.system(cmd)
     if search_log_for_text(config.grepstr, logname):
         print("%s: Success" % config.name)
@@ -91,11 +94,13 @@ def main():
     """Run the tests and count the failures"""
     global configs
     try:
+        os.chdir(regressionDir)
         os.mkdir("logs")
     except:
         pass
 
     if '-makeTests' in sys.argv:
+        os.chdir(regressionDir)
         os.system('./make-tests.sh | tee ./logs/make-tests.log')
 
     if '-all' in sys.argv:
diff --git a/wally-pipelined/src/fpu/fma.sv b/wally-pipelined/src/fpu/fma.sv
index db55ee5c..6ad3f986 100644
--- a/wally-pipelined/src/fpu/fma.sv
+++ b/wally-pipelined/src/fpu/fma.sv
@@ -23,8 +23,11 @@
 ///////////////////////////////////////////
 
 `include "wally-config.vh"
-//    `include "../../../config/rv64icfd/wally-config.vh"
 
+// `define FLEN 64//(`Q_SUPPORTED ? 128 : `D_SUPPORTED ? 64 : 32)
+// `define NE   11//(`Q_SUPPORTED ? 15 : `D_SUPPORTED ? 11 : 8)
+// `define NF   52//(`Q_SUPPORTED ? 112 : `D_SUPPORTED ? 52 : 23)
+// `define XLEN 64
 module fma(
     input logic                 clk,
     input logic                 reset,
@@ -113,7 +116,7 @@ module fma1(
     logic [3*`NF+5:0]   AlignedAddendE;     // Z aligned for addition in U(NF+5.2NF+1)
     logic [3*`NF+6:0]   AlignedAddendInv;   // aligned addend possibly inverted
     logic [2*`NF+1:0]   ProdManKilled;      // the product's mantissa possibly killed
-    logic [3*`NF+6:0]   NegProdManKilled;   // a negated ProdManKilled
+    logic [3*`NF+4:0]   NegProdManKilled;   // a negated ProdManKilled
     logic [8:0]         PNormCnt, NNormCnt; // the positive and nagitive LOA results
     logic [3*`NF+6:0]   PreSum, NegPreSum;  // positive and negitve versions of the sum
 
@@ -149,11 +152,11 @@ module fma1(
         
     add add(.AlignedAddendE, .ProdManE, .PSgnE, .ZSgnEffE, .KillProdE, .AlignedAddendInv, .ProdManKilled, .NegProdManKilled, .NegSumE, .PreSum, .NegPreSum, .InvZE, .XZeroE, .YZeroE);
     
-    loa loa(.AlignedAddendE, .AlignedAddendInv, .ProdManKilled, .NegProdManKilled, .PNormCnt, .NNormCnt);
+    loa loa(.A(AlignedAddendInv+{162'b0,InvZE}), .P(ProdManKilled), .NegSumE, .NormCntE);
 
     // Choose the positive sum and accompanying LZA result.
     assign SumE = NegSumE ? NegPreSum[3*`NF+5:0] : PreSum[3*`NF+5:0];
-    assign NormCntE = NegSumE ? NNormCnt : PNormCnt;
+    // assign NormCntE = NegSumE ? NNormCnt : PNormCnt;
 
 
 endmodule
@@ -311,7 +314,7 @@ module add(
     input logic                 XZeroE, YZeroE, // is the input zero
     output logic [3*`NF+6:0] AlignedAddendInv,  // aligned addend possibly inverted
     output logic [2*`NF+1:0] ProdManKilled,     // the product's mantissa possibly killed
-    output logic [3*`NF+6:0] NegProdManKilled,  // a negated ProdManKilled
+    output logic [3*`NF+4:0] NegProdManKilled,  // a negated ProdManKilled
     output logic                NegSumE,        // was the sum negitive
     output logic                InvZE,          // do you invert Z
     output logic [3*`NF+6:0]   PreSum, NegPreSum// possibly negitive sum
@@ -327,99 +330,65 @@ module add(
     assign InvZE = ZSgnEffE ^ PSgnE;
 
     // Choose an inverted or non-inverted addend - the one has to be added now for the LZA
-    assign AlignedAddendInv = InvZE ? -{1'b0, AlignedAddendE} : {1'b0, AlignedAddendE};
+    assign AlignedAddendInv = InvZE ? {1'b1, ~AlignedAddendE} : {1'b0, AlignedAddendE};
     // Kill the product if the product is too small to effect the addition (determined in fma1.sv)
     assign ProdManKilled = ProdManE&{2*`NF+2{~KillProdE}};
     // Negate ProdMan for LZA and the negitive sum calculation
-    assign NegProdManKilled = {{`NF+3{~(XZeroE|YZeroE|KillProdE)}}, -ProdManKilled, 2'b0};
+    assign NegProdManKilled = {{`NF+3{~(XZeroE|YZeroE|KillProdE)}}, ~ProdManKilled&{2*`NF+2{~(XZeroE|YZeroE)}}};
 
 
+    // Is the sum negitive
+    assign NegSumE = (AlignedAddendE > {54'b0, ProdManKilled, 2'b0})&InvZE; //***use this to avoid addition and final muxing???
 
     // Do the addition
     //      - calculate a positive and negitive sum in parallel
-    assign PreSum = AlignedAddendInv + {55'b0, ProdManKilled, 2'b0};
-    assign NegPreSum = AlignedAddendE + NegProdManKilled;
+    assign PreSum = AlignedAddendInv + {55'b0, ProdManKilled, 2'b0} + {{3*`NF+6{1'b0}}, InvZE};
+    assign NegPreSum = AlignedAddendE + {NegProdManKilled, 2'b0} + {{(3*`NF+3){1'b0}},~(XZeroE|YZeroE),2'b0};
      
-    // Is the sum negitive
-    assign NegSumE = PreSum[3*`NF+6];
 
 endmodule
 
 
-module loa(
-    input logic [3*`NF+5:0] AlignedAddendE,     // Z aligned for addition in U(NF+5.2NF+1)
-    input logic [3*`NF+6:0] AlignedAddendInv,   // aligned addend possibly inverted
-    input logic [2*`NF+1:0] ProdManKilled,      // the product's mantissa possibly killed
-    input logic [3*`NF+6:0] NegProdManKilled,   // a negated ProdManKilled
-    output logic [8:0]      PNormCnt, NNormCnt  // positive and negitive LOA result    
-);
-
-    // LZAs one for the positive result and one for the negitive
-    //      - the +1 from inverting causes problems for normalization
-    posloa posloa(AlignedAddendInv, ProdManKilled, PNormCnt);
-    negloa negloa({1'b0,AlignedAddendE}, NegProdManKilled, NNormCnt);
-
-endmodule
-
-
-module posloa(
+module loa( //https://ieeexplore.ieee.org/abstract/document/930098
     input logic  [3*`NF+6:0] A,     // addend
     input logic  [2*`NF+1:0] P,     // product
-    output logic [8:0]       PCnt   // normalization shift count for the positive result
+    input logic              NegSumE, // is the sum negitive
+    output logic [8:0]       NormCntE   // normalization shift count for the positive result
     ); 
     
 
-    // calculate the propagate (T) and kill (Z) bits
     logic [3*`NF+6:0] T;
+    logic [3*`NF+5:0] G;
     logic [3*`NF+5:0] Z;
     assign T[3*`NF+6:2*`NF+4] = A[3*`NF+6:2*`NF+4];
-    assign Z[3*`NF+5:2*`NF+4] = A[3*`NF+5:2*`NF+4];
+    assign G[3*`NF+5:2*`NF+4] = 0;
+    assign Z[3*`NF+5:2*`NF+4] = ~A[3*`NF+5:2*`NF+4];
     assign T[2*`NF+3:2] = A[2*`NF+3:2]^P;
-    assign Z[2*`NF+3:2] = A[2*`NF+3:2]|P;
+    assign G[2*`NF+3:2] = A[2*`NF+3:2]&P;
+    assign Z[2*`NF+3:2] = ~A[2*`NF+3:2]&~P;
     assign T[1:0] = A[1:0];
-    assign Z[1:0] = A[1:0];
+    assign G[1:0] = 0;
+    assign Z[1:0] = ~A[1:0];
     
 
     // Apply function to determine Leading pattern
     logic [3*`NF+6:0] f;
-    assign f = T^{Z[3*`NF+5:0], 1'b0};
+    assign f = NegSumE ? T^{~G[3*`NF+5:0],1'b1} : T^{~Z[3*`NF+5:0], 1'b1};
 
-    lzc lzc(.f, .Cnt(PCnt));
+    lzc lzc(.f, .NormCntE);
   
 endmodule
 
-module negloa(
-    input logic  [3*`NF+6:0]    A,      // addend
-    input logic  [3*`NF+6:0]    P,      // product
-    output logic [8:0]          NCnt    // normalization shift count for the negitive result
-    ); 
-    
-    // calculate the propagate (T) and kill (Z) bits
-    logic [3*`NF+6:0] T;
-    logic [3*`NF+5:0] Z;
-    assign T = A^P;
-    assign Z = ~(A[3*`NF+5:0]|P[3*`NF+5:0]);
-    
-
-    // Apply function to determine Leading pattern
-    logic [3*`NF+6:0] f;
-    assign f = T^{~Z, 1'b0};
-    
-    lzc lzc(.f, .Cnt(NCnt));
-  
-endmodule
-
-
 module lzc(
     input logic  [3*`NF+6:0]    f,
-    output logic [8:0]          Cnt    // normalization shift count for the negitive result
+    output logic [8:0]          NormCntE    // normalization shift
 );
     
     logic [8:0] i;
     always_comb begin
         i = 0;
         while (~f[3*`NF+6-i] && $unsigned(i) <= $unsigned(9'd3*9'd`NF+9'd6)) i = i+1;  // search for leading one
-        Cnt = i;
+        NormCntE = i;
     end
 endmodule
 
@@ -479,7 +448,7 @@ module fma2(
     // Normalization
     ///////////////////////////////////////////////////////////////////////////////
 
-    normalize normalize(.SumM, .ZExpM, .ProdExpM, .NormCntM, .FmtM, .KillProdM, .AddendStickyM, .NormSum,
+    normalize normalize(.SumM, .ZExpM, .ProdExpM, .NormCntM, .FmtM, .KillProdM, .AddendStickyM, .NormSum, .NegSumM,
             .SumZero, .NormSumSticky, .UfSticky, .SumExp, .ResultDenorm);
 
 
@@ -611,6 +580,80 @@ module resultselect(
 endmodule
 
 
+// module normalize(
+//     input logic  [3*`NF+5:0]    SumM,       // the positive sum
+//     input logic  [`NE-1:0]      ZExpM,      // exponent of Z
+//     input logic  [`NE+1:0]      ProdExpM,   // X exponent + Y exponent - bias
+//     input logic  [8:0]          NormCntM,   // normalization shift count
+//     input logic                 FmtM,       // precision 1 = double 0 = single
+//     input logic                 KillProdM,  // is the product set to zero
+//     input logic                 AddendStickyM,  // the sticky bit caclulated from the aligned addend
+//     input logic                 NegSumM,    // was the sum negitive
+//     output logic [`NF+2:0]      NormSum,        // normalized sum
+//     output logic                SumZero,        // is the sum zero
+//     output logic                NormSumSticky, UfSticky,    // sticky bits
+//     output logic [`NE+1:0]      SumExp,         // exponent of the normalized sum
+//     output logic                ResultDenorm    // is the result denormalized
+// );
+//     logic [`NE+1:0]     FracLen;            // length of the fraction
+//     logic [`NE+1:0]     SumExpTmp;          // exponent of the normalized sum not taking into account denormal or zero results
+//     logic [8:0]         DenormShift;        // right shift if the result is denormalized //***change this later
+//     logic [3*`NF+5:0]   CorrSumShifted;     // the shifted sum after LZA correction
+//     logic [3*`NF+7:0]   SumShifted;         // the shifted sum before LZA correction
+//     logic [`NE+1:0]     SumExpTmpTmp;       // the exponent of the normalized sum with the `FLEN bias
+//     logic               PreResultDenorm;    // is the result denormalized - calculated before LZA corection
+//     logic               PreResultDenorm2;    // is the result denormalized - calculated before LZA corection
+//     logic               LZAPlus1;           // add one to the sum's exponent due to LZA correction
+
+//     ///////////////////////////////////////////////////////////////////////////////
+//     // Normalization
+//     ///////////////////////////////////////////////////////////////////////////////
+
+//     // Determine if the sum is zero
+//     assign SumZero = ~(|SumM);
+
+//     // determine the length of the fraction based on precision
+//     assign FracLen = FmtM ? `NF+1 : 13'd24;
+
+//     // calculate the sum's exponent
+//     assign SumExpTmpTmp = KillProdM ? {2'b0, ZExpM} : ProdExpM + -({4'b0, NormCntM} + 1 - (`NF+4)); // ****try moving this into previous stage
+//     assign SumExpTmp = FmtM ? SumExpTmpTmp : (SumExpTmpTmp-1023+127)&{`NE+2{|SumExpTmpTmp}}; // ***move this ^ the subtraction by a constant isn't simplified
+    
+//     logic SumDLTEZ, SumDGEFL, SumSLTEZ, SumSGEFL;
+//     assign SumDLTEZ = SumExpTmpTmp[`NE+1] | ~|SumExpTmpTmp;
+//     assign SumDGEFL = ($signed(SumExpTmpTmp)>=$signed(-(13'd`NF+13'd1)));
+//     assign SumSLTEZ = $signed(SumExpTmpTmp) <= $signed(13'd1023-13'd127);
+//     assign SumSGEFL = ($signed(SumExpTmpTmp)>=$signed(-13'd24+13'd1023-13'd127)) | ~|SumExpTmpTmp;
+//     assign PreResultDenorm2 = (FmtM ? SumDLTEZ : SumSLTEZ) & (FmtM ? SumDGEFL : SumSGEFL) & ~SumZero; //***make sure math good
+//     // always_comb begin
+//     //     assert (PreResultDenorm == PreResultDenorm2) else $fatal ("PreResultDenorms not equal");
+//     // end
+
+
+
+//     // Determine if the result is denormal
+//     // assign PreResultDenorm = $signed(SumExpTmp)<=0 & ($signed(SumExpTmp)>=$signed(-FracLen)) & ~SumZero;
+
+//     // Determine the shift needed for denormal results
+//     //  - if not denorm add 1 to shift out the leading 1
+//     assign DenormShift = PreResultDenorm2 ? SumExpTmp[8:0] : 1; //*** change this when changing the size of DenormShift also change to an and opperation
+//     // Normalize the sum
+//     assign SumShifted = {2'b0, SumM} << NormCntM+DenormShift; //*** fix mux's with constants in them //***NormCnt can be simplified
+//     // LZA correction
+//     assign LZAPlus1 = SumShifted[3*`NF+7];
+//     assign CorrSumShifted =  LZAPlus1 ? SumShifted[3*`NF+6:1] : SumShifted[3*`NF+5:0];
+//     assign NormSum = CorrSumShifted[3*`NF+5:2*`NF+3];
+//     // Calculate the sticky bit
+//     assign NormSumSticky = (|CorrSumShifted[2*`NF+2:0]) | (|CorrSumShifted[136:2*`NF+3]&~FmtM);
+//     assign UfSticky = AddendStickyM | NormSumSticky;
+
+//     // Determine sum's exponent
+//     assign SumExp = (SumExpTmp+{12'b0, LZAPlus1}+{12'b0, ~|SumExpTmp&SumShifted[3*`NF+6]}) & {`NE+2{~(SumZero|ResultDenorm)}};
+//     // recalculate if the result is denormalized
+//     assign ResultDenorm = PreResultDenorm2&~SumShifted[3*`NF+6]&~SumShifted[3*`NF+7];
+
+// endmodule
+
 module normalize(
     input logic  [3*`NF+5:0]    SumM,       // the positive sum
     input logic  [`NE-1:0]      ZExpM,      // exponent of Z
@@ -619,6 +662,7 @@ module normalize(
     input logic                 FmtM,       // precision 1 = double 0 = single
     input logic                 KillProdM,  // is the product set to zero
     input logic                 AddendStickyM,  // the sticky bit caclulated from the aligned addend
+    input logic                 NegSumM,    // was the sum negitive
     output logic [`NF+2:0]      NormSum,        // normalized sum
     output logic                SumZero,        // is the sum zero
     output logic                NormSumSticky, UfSticky,    // sticky bits
@@ -629,15 +673,29 @@ module normalize(
     logic [`NE+1:0]     SumExpTmp;          // exponent of the normalized sum not taking into account denormal or zero results
     logic [8:0]         DenormShift;        // right shift if the result is denormalized //***change this later
     logic [3*`NF+5:0]   CorrSumShifted;     // the shifted sum after LZA correction
-    logic [3*`NF+7:0]   SumShifted;         // the shifted sum before LZA correction
+    logic [3*`NF+8:0]   SumShifted;         // the shifted sum before LZA correction
     logic [`NE+1:0]     SumExpTmpTmp;       // the exponent of the normalized sum with the `FLEN bias
     logic               PreResultDenorm;    // is the result denormalized - calculated before LZA corection
-    logic               LZAPlus1;           // add one to the sum's exponent due to LZA correction
+    logic               PreResultDenorm2;   // is the result denormalized - calculated before LZA corection
+    logic               LZAPlus1, LZAPlus2; // add one or two to the sum's exponent due to LZA correction
 
     ///////////////////////////////////////////////////////////////////////////////
     // Normalization
     ///////////////////////////////////////////////////////////////////////////////
 
+
+    // logic [8:0] supposedNormCnt;
+    // logic [8:0] i;
+    // always_comb begin
+    //         i = 0;
+    //         while (~SumM[3*`NF+5-i] && $unsigned(i) <= $unsigned(3*`NF+5)) i = i+1;  // search for leading one
+    //         supposedNormCnt = i;    // compute shift count
+    // end
+
+    // always_comb begin
+    //     assert (NormCntM == supposedNormCnt | NormCntM == supposedNormCnt+1 | NormCntM == supposedNormCnt+2) else $fatal ("normcnt not expected");
+    // end
+
     // Determine if the sum is zero
     assign SumZero = ~(|SumM);
 
@@ -645,19 +703,36 @@ module normalize(
     assign FracLen = FmtM ? `NF+1 : 13'd24;
 
     // calculate the sum's exponent
-    assign SumExpTmpTmp = KillProdM ? {2'b0, ZExpM} : ProdExpM + -({4'b0, NormCntM} + 1 - (`NF+4));
-    assign SumExpTmp = FmtM ? SumExpTmpTmp : (SumExpTmpTmp-1023+127)&{`NE+2{|SumExpTmpTmp}};
+    assign SumExpTmpTmp = KillProdM ? {2'b0, ZExpM} : ProdExpM + -({4'b0, NormCntM} + 1 - (`NF+4)); // ****try moving this into previous stage
+    assign SumExpTmp = FmtM ? SumExpTmpTmp : (SumExpTmpTmp-1023+127)&{`NE+2{|SumExpTmpTmp}}; // ***move this ^ the subtraction by a constant isn't simplified
+    
+    logic SumDLTEZ, SumDGEFL, SumSLTEZ, SumSGEFL;
+    assign SumDLTEZ = SumExpTmpTmp[`NE+1] | ~|SumExpTmpTmp;
+    assign SumDGEFL = ($signed(SumExpTmpTmp)>=$signed(-(13'd`NF+13'd1)));
+    assign SumSLTEZ = $signed(SumExpTmpTmp) <= $signed(13'd1023-13'd127);
+    assign SumSGEFL = ($signed(SumExpTmpTmp)>=$signed(-13'd24+13'd1023-13'd127)) | ~|SumExpTmpTmp;
+    assign PreResultDenorm2 = (FmtM ? SumDLTEZ : SumSLTEZ) & (FmtM ? SumDGEFL : SumSGEFL) & ~SumZero; //***make sure math good
+    // always_comb begin
+    //     assert (PreResultDenorm == PreResultDenorm2) else $fatal ("PreResultDenorms not equal");
+    // end
+
+    // 010. when should be 001.
+    //      - shift left one
+    //      - add one from exp
+    //      - if kill prod dont add to exp
 
     // Determine if the result is denormal
-    assign PreResultDenorm = $signed(SumExpTmp)<=0 & ($signed(SumExpTmp)>=$signed(-FracLen)) & ~SumZero;
+    // assign PreResultDenorm = $signed(SumExpTmp)<=0 & ($signed(SumExpTmp)>=$signed(-FracLen)) & ~SumZero;
 
     // Determine the shift needed for denormal results
     //  - if not denorm add 1 to shift out the leading 1
-    assign DenormShift = PreResultDenorm ? SumExpTmp[8:0] : 1; //*** change this when changing the size of DenormShift also change to an and opperation
+    assign DenormShift = PreResultDenorm2 ? SumExpTmp[8:0] : 1; //*** change this when changing the size of DenormShift also change to an and opperation
     // Normalize the sum
-    assign SumShifted = {2'b0, SumM} << NormCntM+DenormShift; //*** fix mux's with constants in them //***NormCnt can be simplified
+    assign SumShifted = {3'b0, SumM} << NormCntM+DenormShift; //*** fix mux's with constants in them //***NormCnt can be simplified
     // LZA correction
     assign LZAPlus1 = SumShifted[3*`NF+7];
+    assign LZAPlus2 = SumShifted[3*`NF+8];
+	// the only possible mantissa for a plus two is all zeroes - a one has to propigate all the way through a sum. so we can leave the bottom statement alone
     assign CorrSumShifted =  LZAPlus1 ? SumShifted[3*`NF+6:1] : SumShifted[3*`NF+5:0];
     assign NormSum = CorrSumShifted[3*`NF+5:2*`NF+3];
     // Calculate the sticky bit
@@ -665,9 +740,10 @@ module normalize(
     assign UfSticky = AddendStickyM | NormSumSticky;
 
     // Determine sum's exponent
-    assign SumExp = (SumExpTmp+{12'b0, LZAPlus1}+{12'b0, ~|SumExpTmp&SumShifted[3*`NF+6]}) & {`NE+2{~(SumZero|ResultDenorm)}};
+    //                          if plus1                     If plus2                                      if said denorm but norm plus 1     if said denorm (-1 val) but norm plus 2
+    assign SumExp = (SumExpTmp+{12'b0, LZAPlus1&~KillProdM}+{11'b0, LZAPlus2&~KillProdM, 1'b0}+{12'b0, ~|SumExpTmp&SumShifted[3*`NF+6]&~KillProdM}+{11'b0, &SumExpTmp&SumShifted[3*`NF+6]&~KillProdM, 1'b0}) & {`NE+2{~(SumZero|ResultDenorm)}};
     // recalculate if the result is denormalized
-    assign ResultDenorm = PreResultDenorm&~SumShifted[3*`NF+6]&~SumShifted[3*`NF+7];
+    assign ResultDenorm = PreResultDenorm2&~SumShifted[3*`NF+6]&~SumShifted[3*`NF+7];
 
 endmodule
 
diff --git a/wally-pipelined/src/ieu/datapath.sv b/wally-pipelined/src/ieu/datapath.sv
index 838d83a7..0679f8c3 100644
--- a/wally-pipelined/src/ieu/datapath.sv
+++ b/wally-pipelined/src/ieu/datapath.sv
@@ -96,7 +96,7 @@ module datapath (
   //Mux for writting floating point 
   
   regfile regf(clk, reset, {RegWriteW | FWriteIntW}, Rs1D, Rs2D, RdW, WriteDataW, RD1D, RD2D);
-  extend ext(.InstrD(InstrD[31:7]), .*);
+  extend ext(.InstrD(InstrD[31:7]), .ImmSrcD, .ExtImmD);
  
   // Execute stage pipeline register and logic
   flopenrc #(`XLEN) RD1EReg(clk, reset, FlushE, ~StallE, RD1D, RD1E);
diff --git a/wally-pipelined/src/ieu/ieu.sv b/wally-pipelined/src/ieu/ieu.sv
index e9c6d117..06849522 100644
--- a/wally-pipelined/src/ieu/ieu.sv
+++ b/wally-pipelined/src/ieu/ieu.sv
@@ -90,9 +90,69 @@ module ieu (
   logic             MemReadE, CSRReadE;
   logic             JumpE;
            
-  controller c(.*);
-  datapath   dp(.*);             
-  forward    fw(.*);
+  controller c(
+    .clk, .reset,
+    // Decode stage control signals
+    .StallD, .FlushD, .InstrD, .ImmSrcD,
+    .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD,
+    // Execute stage control signals
+    .StallE, .FlushE, .FlagsE, 
+    .PCSrcE,        // for datapath and Hazard Unit
+    .ALUControlE, .ALUSrcAE, .ALUSrcBE,
+    .TargetSrcE,
+    .MemReadE, .CSRReadE, // for Hazard Unit
+    .Funct3E, .MulDivE, .W64E,
+    .JumpE,	
+    // Memory stage control signals
+    .StallM, .FlushM, .MemRWM,
+    .CSRReadM, .CSRWriteM, .PrivilegedM,
+    .SCE, .AtomicE, .AtomicM, .Funct3M,
+    .RegWriteM,     // for Hazard Unit
+    .InvalidateICacheM, .FlushDCacheM, .InstrValidM, 
+    // Writeback stage control signals
+    .StallW, .FlushW,
+    .RegWriteW,     // for datapath and Hazard Unit
+    .ResultSrcW,
+    // Stall during CSRs
+    .CSRWritePendingDEM,
+    .StoreStallD
+  );
+
+  datapath   dp(
+    .clk, .reset,
+    // Decode stage signals
+    .ImmSrcD, .InstrD,
+    // Execute stage signals
+    .StallE, .FlushE, .ForwardAE, .ForwardBE,
+    .ALUControlE, .ALUSrcAE, .ALUSrcBE,
+    .TargetSrcE, .JumpE, .IllegalFPUInstrE,
+    .FWriteDataE, .PCE, .PCLinkE, .FlagsE,
+    .PCTargetE,
+    .ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
+    .SrcAE, .SrcBE,
+    // Memory stage signals
+    .StallM, .FlushM, .FWriteIntM, .FIntResM, 
+    .SrcAM, .WriteDataM, .MemAdrM, .MemAdrE,
+    // Writeback stage signals
+    .StallW, .FlushW, .FWriteIntW, .RegWriteW, 
+    .SquashSCW, .ResultSrcW, .ReadDataW,
+    // input  logic [`XLEN-1:0] PCLinkW,
+    .CSRReadValW, .ReadDataM, .MulDivResultW, 
+    // Hazard Unit signals 
+    .Rs1D, .Rs2D, .Rs1E, .Rs2E,
+    .RdE, .RdM, .RdW 
+  );             
+  
+  forward    fw(
+    .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW,
+    .MemReadE, .MulDivE, .CSRReadE,
+    .RegWriteM, .RegWriteW,
+    .FWriteIntE, .FWriteIntM, .FWriteIntW,
+    .SCE,
+    // Forwarding controls
+    .ForwardAE, .ForwardBE,
+    .FPUStallD, .LoadStallD, .MulDivStallD, .CSRRdStallD
+    );
 
 endmodule
 
diff --git a/wally-pipelined/src/sdc/sd_dat_fsm.sv b/wally-pipelined/src/sdc/sd_dat_fsm.sv
index 124d6551..7726f1cb 100644
--- a/wally-pipelined/src/sdc/sd_dat_fsm.sv
+++ b/wally-pipelined/src/sdc/sd_dat_fsm.sv
@@ -64,7 +64,6 @@ module sd_dat_fsm
   (* mark_debug = "true" *) logic [3:0] 	r_curr_state;
    logic [3:0] 	w_next_state;  
   
-  (* mark_debug = "true" *) logic w_error_crc16_fd_en, w_error_crc16_fd_rst, w_error_crc16_fd_d; // Save ERROR_CRC16 so CMD FSM sees it in IDLE_NRC (not just in IDLE_DAT)
   logic r_error_crc16_fd_Q;
 
   logic [22:0] Identify_Timer_In;
diff --git a/wally-pipelined/src/uncore/dtim.sv b/wally-pipelined/src/uncore/dtim.sv
index 0ebededc..59beebb6 100644
--- a/wally-pipelined/src/uncore/dtim.sv
+++ b/wally-pipelined/src/uncore/dtim.sv
@@ -49,54 +49,56 @@ module dtim #(parameter BASE=0, RANGE = 65535, string PRELOAD="") (
   logic        memwrite;
   logic [3:0]  busycount;
 
-  initial begin
-    //$readmemh(PRELOAD, RAM);
-/* -----\/----- EXCLUDED -----\/-----
- // FPGA only
-    RAM[0] =  64'h94e1819300002197;
-    RAM[1] =  64'h4281420141014081;
-    RAM[2] =  64'h4481440143814301;
-    RAM[3] =  64'h4681460145814501;
-    RAM[4] =  64'h4881480147814701;
-    RAM[5] =  64'h4a814a0149814901;
-    RAM[6] =  64'h4c814c014b814b01;
-    RAM[7] =  64'h4e814e014d814d01;
-    RAM[8] =  64'h0110011b4f814f01;
-    RAM[9] =  64'h059b45011161016e;
-    RAM[10] = 64'h0004063705fe0010;
-    RAM[11] = 64'h05a000ef8006061b;
-    RAM[12] = 64'h0ff003930000100f;
-    RAM[13] = 64'h4e952e3110012e37;
-    RAM[14] = 64'hc602829b0053f2b7;
-    RAM[15] = 64'h2023fe02dfe312fd;
-    RAM[16] = 64'h829b0053f2b7007e;
-    RAM[17] = 64'hfe02dfe312fdc602;
-    RAM[18] = 64'h4de31efd000e2023;
-    RAM[19] = 64'h059bf1402573fdd0;
-    RAM[20] = 64'h0000061705e20870;
-    RAM[21] = 64'h0010029b01260613;
-    RAM[22] = 64'h11010002806702fe;
-    RAM[23] = 64'h84b2842ae426e822;
-    RAM[24] = 64'h892ee04aec064505;
-    RAM[25] = 64'h06e000ef07e000ef;
-    RAM[26] = 64'h979334fd02905563;
-    RAM[27] = 64'h07930177d4930204;
-    RAM[28] = 64'h4089093394be2004;
-    RAM[29] = 64'h04138522008905b3;
-    RAM[30] = 64'h19e3014000ef2004;
-    RAM[31] = 64'h64a2644260e2fe94;
-    RAM[32] = 64'h6749808261056902;
-    RAM[33] = 64'hdfed8b8510472783;
-    RAM[34] = 64'h2423479110a73823;
-    RAM[35] = 64'h10472783674910f7;
-    RAM[36] = 64'h20058693ffed8b89;
-    RAM[37] = 64'h05a1118737836749;
-    RAM[38] = 64'hfed59be3fef5bc23;
-    RAM[39] = 64'h1047278367498082;
-    RAM[40] = 64'h67c98082dfed8b85;
-    RAM[41] = 64'h0000808210a7a023;
- -----/\----- EXCLUDED -----/\----- */
-  end
+  generate
+    if(`FPGA) begin
+      initial begin
+	//$readmemh(PRELOAD, RAM);
+	// FPGA only
+	RAM[0] =  64'h94e1819300002197;
+	RAM[1] =  64'h4281420141014081;
+	RAM[2] =  64'h4481440143814301;
+	RAM[3] =  64'h4681460145814501;
+	RAM[4] =  64'h4881480147814701;
+	RAM[5] =  64'h4a814a0149814901;
+	RAM[6] =  64'h4c814c014b814b01;
+	RAM[7] =  64'h4e814e014d814d01;
+	RAM[8] =  64'h0110011b4f814f01;
+	RAM[9] =  64'h059b45011161016e;
+	RAM[10] = 64'h0004063705fe0010;
+	RAM[11] = 64'h05a000ef8006061b;
+	RAM[12] = 64'h0ff003930000100f;
+	RAM[13] = 64'h4e952e3110012e37;
+	RAM[14] = 64'hc602829b0053f2b7;
+	RAM[15] = 64'h2023fe02dfe312fd;
+	RAM[16] = 64'h829b0053f2b7007e;
+	RAM[17] = 64'hfe02dfe312fdc602;
+	RAM[18] = 64'h4de31efd000e2023;
+	RAM[19] = 64'h059bf1402573fdd0;
+	RAM[20] = 64'h0000061705e20870;
+	RAM[21] = 64'h0010029b01260613;
+	RAM[22] = 64'h11010002806702fe;
+	RAM[23] = 64'h84b2842ae426e822;
+	RAM[24] = 64'h892ee04aec064505;
+	RAM[25] = 64'h06e000ef07e000ef;
+	RAM[26] = 64'h979334fd02905563;
+	RAM[27] = 64'h07930177d4930204;
+	RAM[28] = 64'h4089093394be2004;
+	RAM[29] = 64'h04138522008905b3;
+	RAM[30] = 64'h19e3014000ef2004;
+	RAM[31] = 64'h64a2644260e2fe94;
+	RAM[32] = 64'h6749808261056902;
+	RAM[33] = 64'hdfed8b8510472783;
+	RAM[34] = 64'h2423479110a73823;
+	RAM[35] = 64'h10472783674910f7;
+	RAM[36] = 64'h20058693ffed8b89;
+	RAM[37] = 64'h05a1118737836749;
+	RAM[38] = 64'hfed59be3fef5bc23;
+	RAM[39] = 64'h1047278367498082;
+	RAM[40] = 64'h67c98082dfed8b85;
+	RAM[41] = 64'h0000808210a7a023;
+      end // initial begin
+    end // if (FPGA)
+  endgenerate
 
   assign initTrans = HREADY & HSELTim & (HTRANS != 2'b00);
 
diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv
index 50559b9d..a757e4f7 100644
--- a/wally-pipelined/testbench/testbench-linux.sv
+++ b/wally-pipelined/testbench/testbench-linux.sv
@@ -48,7 +48,7 @@ module testbench();
   ///////////////////////////////////////////////////////////////////////////////
   ////////////////////////////////// HARDWARE ///////////////////////////////////
   ///////////////////////////////////////////////////////////////////////////////
-  logic clk, reset, reset_ext; 
+  logic clk, reset_ext; 
   initial begin reset_ext <= 1; # 22; reset_ext <= 0; end
   always begin clk <= 1; # 5; clk <= 0; # 5; end
 
@@ -85,6 +85,9 @@ module testbench();
                         .UARTSin, .UARTSout,
 			.SDCCLK, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn);
 
+  logic reset;
+  assign reset = dut.reset;
+
   // Write Back stage signals not needed by Wally itself 
   parameter nop = 'h13;
   logic [`XLEN-1:0] PCW;