diff --git a/wally-pipelined/src/mmu/hptw.sv b/wally-pipelined/src/mmu/hptw.sv
index 845f495d..fd7cee43 100644
--- a/wally-pipelined/src/mmu/hptw.sv
+++ b/wally-pipelined/src/mmu/hptw.sv
@@ -48,6 +48,12 @@ module hptw
    output logic		    WalkerInstrPageFaultF, WalkerLoadPageFaultM,WalkerStorePageFaultM // faults
 );
 
+      typedef enum  {L0_ADR, L0_RD, 
+				     L1_ADR, L1_RD, 
+				     L2_ADR, L2_RD, 
+				     L3_ADR, L3_RD, 
+				     LEAF, IDLE, FAULT} statetype; // *** placed outside generate statement to remove synthesis errors
+
   generate
     if (`MEM_VIRTMEM) begin
       logic			    DTLBWalk; // register TLBs translation miss requests
@@ -64,12 +70,6 @@ module hptw
       logic [`SVMODE_BITS-1:0]	    SvMode;
       logic [`XLEN-1:0] 	    TranslationVAdr;
       
-
-      typedef enum  {L0_ADR, L0_RD, 
-				     L1_ADR, L1_RD, 
-				     L2_ADR, L2_RD, 
-				     L3_ADR, L3_RD, 
-				     LEAF, IDLE, FAULT} statetype;
       statetype WalkerState, NextWalkerState, InitialWalkerState;
 
 	  // Extract bits from CSRs and inputs
diff --git a/wally-pipelined/src/mmu/pmpadrdec.sv b/wally-pipelined/src/mmu/pmpadrdec.sv
index 0fe2b2d7..61816782 100644
--- a/wally-pipelined/src/mmu/pmpadrdec.sv
+++ b/wally-pipelined/src/mmu/pmpadrdec.sv
@@ -67,9 +67,7 @@ module pmpadrdec (
   assign TORMatch = PAgePMPAdrIn && PAltPMPAdr;
 
   // Naturally aligned regions
-
-  // verilator lint_off UNOPTFLAT
-  logic [`PA_BITS-1:0] Mask;
+  logic [`PA_BITS-1:0] NAMask;
   //genvar i;
   
   // create a mask of which bits to ignore
@@ -80,23 +78,14 @@ module pmpadrdec (
   //     assign Mask[i] = Mask[i-1] & PMPAdr[i-3]; // NAPOT mask: 1's indicate bits to ignore
   //   end
   // endgenerate
-  prioritycircuit #(.ENTRIES(`PA_BITS-2), .FINAL_OP("NONE")) maskgen(.a(~PMPAdr[`PA_BITS-3:0]), .FirstPin(AdrMode==NAPOT), .y(Mask[`PA_BITS-1:2]));
-  assign Mask[1:0] = 2'b11;
 
-  // *** possible experiments:
-  /* PA < PMP addr could be in its own module, 
-        preeserving hierarchy so we can know if this is the culprit on the critical path
-        Should take logarthmic time, so more like 6 levels than 40 should be expected
+  assign NAMask[1:0] = {2'b11};
 
-    update mask generation
-        Should be concurrent with the subtraction/comparison
-        if one is the critical path, the other shouldn't be which makes us think the mask generation is the culprit.
+  prioritythemometer #(`PA_BITS-2) namaskgen(
+    .a({PMPAdr[`PA_BITS-4:0], (AdrMode == NAPOT)}),
+    .y(NAMask[`PA_BITS-1:2]));
 
-    Hopefully just use the priority circuit here
-    */
-  // verilator lint_on UNOPTFLAT
-
-  assign NAMatch = &((PhysicalAddress ~^ CurrentAdrFull) | Mask);
+  assign NAMatch = &((PhysicalAddress ~^ CurrentAdrFull) | NAMask);
 
   assign Match = (AdrMode == TOR) ? TORMatch : 
                  (AdrMode == NA4 || AdrMode == NAPOT) ? NAMatch :
diff --git a/wally-pipelined/src/mmu/pmpchecker.sv b/wally-pipelined/src/mmu/pmpchecker.sv
index eac4cc47..7dc37163 100644
--- a/wally-pipelined/src/mmu/pmpchecker.sv
+++ b/wally-pipelined/src/mmu/pmpchecker.sv
@@ -69,7 +69,7 @@ module pmpchecker (
     .PAgePMPAdrOut(PAgePMPAdr),
     .FirstMatch, .Match, .Active, .L, .X, .W, .R);
 
-  prioritycircuit #(.ENTRIES(`PMP_ENTRIES), .FINAL_OP("AND")) pmppriority(.a(Match), .FirstPin(1'b1), .y(FirstMatch)); // Take the ripple gates/signals out of the pmpadrdec and into another unit.
+  priorityonehot #(`PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // Take the ripple gates/signals out of the pmpadrdec and into another unit.
 
   // Only enforce PMP checking for S and U modes when at least one PMP is active or in Machine mode when L bit is set in selected region
   assign EnforcePMP = (PrivilegeModeW == `M_MODE) ? |L : |Active; 
diff --git a/wally-pipelined/src/mmu/prioritycircuit.sv b/wally-pipelined/src/mmu/priorityonehot.sv
similarity index 78%
rename from wally-pipelined/src/mmu/prioritycircuit.sv
rename to wally-pipelined/src/mmu/priorityonehot.sv
index df44b35f..75825dc4 100644
--- a/wally-pipelined/src/mmu/prioritycircuit.sv
+++ b/wally-pipelined/src/mmu/priorityonehot.sv
@@ -1,5 +1,5 @@
 ///////////////////////////////////////////
-// prioritycircuit.sv
+// priorityonehot.sv
 //
 // Written: tfleming@hmc.edu & jtorrey@hmc.edu 7 April 2021
 // Modified: Teo Ene 15 Apr 2021:
@@ -30,31 +30,22 @@
 
 `include "wally-config.vh"
 
-module prioritycircuit #(parameter ENTRIES = 8,
-                         parameter FINAL_OP = "AND") (
+module priorityonehot #(parameter ENTRIES = 8) (
   input  logic  [ENTRIES-1:0] a,
-  input  logic                FirstPin,
   output logic  [ENTRIES-1:0] y
 );
-  // verilator lint_off UNOPTFLAT
+
   logic [ENTRIES-1:0] nolower;
 
   // generate thermometer code mask
   genvar i;
   generate
-    assign nolower[0] = FirstPin;
+    assign nolower[0] = 1'b1;
     for (i=1; i<ENTRIES; i++) begin:therm
       assign nolower[i] = nolower[i-1] & ~a[i-1];
     end
   endgenerate
-  // verilator lint_on UNOPTFLAT
+
+  assign y = a & nolower;
   
-  generate
-    if (FINAL_OP=="AND") begin
-      assign y = a & nolower;
-    end else if (FINAL_OP=="NONE") begin
-      assign y = nolower;
-    end // *** So far these are the only two operations I need to do at the end, but feel free to add more as needed.
-  endgenerate
-  // assign y = a & nolower;
 endmodule
diff --git a/wally-pipelined/src/mmu/prioritythermometer.sv b/wally-pipelined/src/mmu/prioritythermometer.sv
new file mode 100644
index 00000000..132a489c
--- /dev/null
+++ b/wally-pipelined/src/mmu/prioritythermometer.sv
@@ -0,0 +1,50 @@
+///////////////////////////////////////////
+// priritythermometer.sv
+//
+// Written: tfleming@hmc.edu & jtorrey@hmc.edu 7 April 2021
+// Modified: Teo Ene 15 Apr 2021:
+//              Temporarily removed paramterized priority encoder for non-parameterized one
+//              To get synthesis working quickly
+//           Kmacsaigoren@hmc.edu 28 May 2021:
+//              Added working version of parameterized priority encoder. 
+//           David_Harris@Hmc.edu switched to one-hot output
+//
+// Purpose: Priority circuit to choose most significant one-hot output
+//
+// A component of the Wally configurable RISC-V project.
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module prioritythemometer #(parameter N = 8) (
+  input  logic  [N-1:0] a,
+  output logic  [N-1:0] y
+);
+
+  // generate thermometer code mask
+  genvar i;
+  generate
+    assign y[0] = a[0];
+    for (i=1; i<N; i++) begin
+      assign y[i] = y[i-1] & a[i];
+    end
+  endgenerate
+
+endmodule
+
+
+
diff --git a/wally-pipelined/src/mmu/tlblru.sv b/wally-pipelined/src/mmu/tlblru.sv
index 70e15401..544be58e 100644
--- a/wally-pipelined/src/mmu/tlblru.sv
+++ b/wally-pipelined/src/mmu/tlblru.sv
@@ -39,7 +39,7 @@ module tlblru #(parameter TLB_ENTRIES = 8) (
   logic                AllUsed;  // High if the next access causes all RU bits to be 1
 
   // Find the first line not recently used
-  prioritycircuit #(.ENTRIES(TLB_ENTRIES), .FINAL_OP("AND")) nru(.a(~RUBits), .FirstPin(1'b1), .y(WriteLines));
+  priorityonehot #(TLB_ENTRIES) nru(.a(~RUBits), .y(WriteLines));
 
   // Track recently used lines, updating on a CAM Hit or TLB write
   assign WriteEnables = WriteLines & {(TLB_ENTRIES){TLBWrite}};