From f3093ac612fcbb08c8030a638e6b3ae3e781efc4 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 20 Apr 2021 22:06:12 -0500 Subject: [PATCH] Why was the linter messed up? There are a number of combo loops which need fixing outside the icache. They may be fixed in main. We get to instruction address 50 now! --- wally-pipelined/lint-wally | 24 +++++------------------- wally-pipelined/regression/wave.do | 4 ++-- wally-pipelined/src/ifu/icache.sv | 25 ++++++++++++++++++------- 3 files changed, 25 insertions(+), 28 deletions(-) diff --git a/wally-pipelined/lint-wally b/wally-pipelined/lint-wally index 791435ac..9d5a20ba 100755 --- a/wally-pipelined/lint-wally +++ b/wally-pipelined/lint-wally @@ -1,25 +1,11 @@ # check for warnings in Verilog code # The verilator lint tool is faster and better than Modelsim so it is best to run this first. -if [ -n "$1" ]; then - echo "rv64ic linting..." - if verilator --lint-only --top-module "$1" -Iconfig/rv64ic src/*/*.sv; then - echo "rv32ic linting..." - verilator --lint-only --top-module "$1" -Iconfig/rv32ic src/*/*.sv - else - echo "Skipping rv32ic because rv64ic had errors or warnings" - exit 1 - fi -else - echo "rv64ic linting..." - if verilator --lint-only --top-module wallypipelinedsoc -Iconfig/rv64ic src/*/*.sv; then - echo "rv32ic linting..." - verilator --lint-only --top-module wallypipelinedsoc -Iconfig/rv32ic src/*/*.sv - else - echo "Skipping rv32ic because rv64ic had errors or warnings" - exit 1 - fi -fi +echo "rv64ic linting..." +verilator --lint-only --top-module wallypipelinedsoc -Iconfig/rv64ic src/*/*.sv +echo "rv32ic linting..." +verilator --lint-only --top-module wallypipelinedsoc -Iconfig/rv32ic src/*/*.sv +#verilator --lint-only --top-module wallypipelinedsoc -Iconfig/rv64ic src/*/*.sv src/*/div/*.sv # --lint-only just runs lint rather than trying to compile and simulate # -I points to the include directory where files such as `include wally-config.vh are found diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index eeb8a0ba..5174a350 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -210,7 +210,7 @@ add wave -noupdate /testbench/dut/hart/ifu/icache/controller/PCPreFinalF add wave -noupdate /testbench/dut/hart/ifu/icache/controller/ICacheStallF add wave -noupdate /testbench/dut/hart/ifu/icache/controller/SavePC TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {44 ns} 0} {{Cursor 2} {284 ns} 0} +WaveRestoreCursors {{Cursor 2} {44 ns} 0} {{Cursor 2} {566 ns} 0} quietly wave cursor active 2 configure wave -namecolwidth 250 configure wave -valuecolwidth 229 @@ -226,4 +226,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {139 ns} {443 ns} +WaveRestoreZoom {458 ns} {674 ns} diff --git a/wally-pipelined/src/ifu/icache.sv b/wally-pipelined/src/ifu/icache.sv index 8c16b3a9..09dab7a8 100644 --- a/wally-pipelined/src/ifu/icache.sv +++ b/wally-pipelined/src/ifu/icache.sv @@ -361,7 +361,7 @@ module icachecontroller #(parameter LINESIZE = 256) ( UnalignedSelect = 1'b0; CntReset = 1'b0; PreCntEn = 1'b0; - InstrReadF = 1'b0; + //InstrReadF = 1'b0; ICacheMemWriteEnable = 1'b0; spillSave = 1'b0; PCMux = 2'b00; @@ -401,7 +401,7 @@ module icachecontroller #(parameter LINESIZE = 256) ( end STATE_HIT_SPILL_MISS_FETCH_WDV: begin PCMux = 2'b10; - InstrReadF = 1'b1; + //InstrReadF = 1'b1; PreCntEn = 1'b1; if (FetchCountFlag & InstrAckF) begin NextState = STATE_HIT_SPILL_MISS_FETCH_DONE; @@ -424,7 +424,7 @@ module icachecontroller #(parameter LINESIZE = 256) ( // branch 3 miss no spill STATE_MISS_FETCH_WDV: begin PCMux = 2'b01; - InstrReadF = 1'b1; + //InstrReadF = 1'b1; PreCntEn = 1'b1; if (FetchCountFlag & InstrAckF) begin NextState = STATE_MISS_FETCH_DONE; @@ -447,7 +447,7 @@ module icachecontroller #(parameter LINESIZE = 256) ( STATE_MISS_SPILL_FETCH_WDV: begin PCMux = 2'b01; PreCntEn = 1'b1; - InstrReadF = 1'b1; + //InstrReadF = 1'b1; if (FetchCountFlag & InstrAckF) begin NextState = STATE_MISS_SPILL_FETCH_DONE; end else begin @@ -478,7 +478,7 @@ module icachecontroller #(parameter LINESIZE = 256) ( STATE_MISS_SPILL_MISS_FETCH_WDV: begin PCMux = 2'b10; PreCntEn = 1'b1; - InstrReadF = 1'b1; + //InstrReadF = 1'b1; if (FetchCountFlag & InstrAckF) begin NextState = STATE_MISS_SPILL_MISS_FETCH_DONE; end else begin @@ -508,11 +508,16 @@ module icachecontroller #(parameter LINESIZE = 256) ( // stall CPU any time we are not in the ready state. any other state means the // cache is either requesting data from the memory interface or handling a // spill over two cycles. - assign ICacheStallF = ((CurrState != STATE_READY) & hit) | reset_q ? 1'b1 : 1'b0; + assign ICacheStallF = ((CurrState != STATE_READY) | ~hit) | reset_q ? 1'b1 : 1'b0; // save the PC anytime we are in the ready state. The saved value will be used as the PC may not be stable. assign SavePC = (CurrState == STATE_READY) & hit ? 1'b1 : 1'b0; assign CntEn = PreCntEn & InstrAckF; + assign InstrReadF = (CurrState == STATE_HIT_SPILL_MISS_FETCH_WDV) || + (CurrState == STATE_MISS_FETCH_WDV) || + (CurrState == STATE_MISS_SPILL_FETCH_WDV) || + (CurrState == STATE_MISS_SPILL_MISS_FETCH_WDV); + // to compute the fetch address we need to add the bit shifted // counter output to the address. @@ -595,7 +600,13 @@ module icachecontroller #(parameter LINESIZE = 256) ( .q(reset_q)); flopenl #(32) AlignedInstrRawDFlop(clk, reset | reset_q, ~StallD, FinalInstrRawF, NOP, AlignedInstrRawD); - mux2 #(32) InstrRawDMux(AlignedInstrRawD, NOP, FlushD, InstrRawD); + // cannot have this mux as it creates a combo loop. + // This flop doesn't stall if StallF is high because we should output a nop + // when FlushD happens, even if the pipeline is also stalled. + flopr #(1) flushDLastCycleFlop(clk, reset, ~FlushD & (FlushDLastCyclen | ~StallF), FlushDLastCyclen); + mux2 #(32) InstrRawDMux(AlignedInstrRawD, NOP, ~FlushDLastCyclen, InstrRawD); + //assign InstrRawD = AlignedInstrRawD; + assign {ICacheMemReadUpperPAdr, ICacheMemReadLowerAdr} = PCPFinalF;