From f306d2d2e17ca443fa9d7f96bcbc1638367a52d7 Mon Sep 17 00:00:00 2001
From: Noah Boorstin <nboorstin@hmc.edu>
Date: Sun, 28 Feb 2021 20:43:57 +0000
Subject: [PATCH] busybear: start preloading bootmem

---
 wally-pipelined/regression/wally-busybear.do |  7 +++++--
 wally-pipelined/src/uncore/adrdec.sv         |  3 ++-
 wally-pipelined/src/uncore/imem.sv           | 14 +++++++++-----
 3 files changed, 16 insertions(+), 8 deletions(-)

diff --git a/wally-pipelined/regression/wally-busybear.do b/wally-pipelined/regression/wally-busybear.do
index 74f6a9d4..5ff685e1 100644
--- a/wally-pipelined/regression/wally-busybear.do
+++ b/wally-pipelined/regression/wally-busybear.do
@@ -33,8 +33,10 @@ vlog +incdir+../config/busybear ../testbench/*.sv ../src/*/*.sv -suppress 2583
 # remove +acc flag for faster sim during regressions if there is no need to access internal signals
 vopt +acc work.testbench_busybear -o workopt 
 vsim workopt -suppress 8852,12070
-mem load -startaddress 0 -endaddress 1024 -filltype value -fillradix hex -filldata 0 /testbench_busybear/bootram
-mem load -startaddress 0 -i "/courses/e190ax/busybear_boot/bootmem.txt" -format hex /testbench_busybear/bootram
+mem load -startaddress 0 -endaddress 2048 -filltype value -fillradix hex -filldata 0 /testbench_busybear/dut/uncore/bootdtim/RAM
+mem load -startaddress 512 -i "/courses/e190ax/busybear_boot/bootmem.txt" -format hex /testbench_busybear/dut/uncore/bootdtim/RAM
+mem load -startaddress 0 -endaddress 2048 -filltype value -fillradix hex -filldata 0 /testbench_busybear/dut/imem/bootram
+mem load -startaddress 512 -i "/courses/e190ax/busybear_boot/bootmem.txt" -format hex /testbench_busybear/dut/imem/bootram
 mem load -startaddress 0 -endaddress 16777216 -filltype value -fillradix hex -filldata 0 /testbench_busybear/RAM
 mem load -startaddress 0 -i "/courses/e190ax/busybear_boot/ram.txt" -format hex /testbench_busybear/RAM
 
@@ -49,6 +51,7 @@ add wave -hex /testbench_busybear/PCtext
 add wave -hex /testbench_busybear/pcExpected
 add wave -hex /testbench_busybear/dut/hart/ifu/PCF
 add wave -hex /testbench_busybear/dut/hart/ifu/InstrF
+add wave -hex /testbench_busybear/dut/InstrF
 add wave /testbench_busybear/CheckInstrF
 add wave /testbench_busybear/lastCheckInstrF
 add wave /testbench_busybear/speculative
diff --git a/wally-pipelined/src/uncore/adrdec.sv b/wally-pipelined/src/uncore/adrdec.sv
index 7e4423ec..31e18d1e 100644
--- a/wally-pipelined/src/uncore/adrdec.sv
+++ b/wally-pipelined/src/uncore/adrdec.sv
@@ -38,7 +38,8 @@ module adrdec (
   // then anything address between 0x04002000 and 0x04002FFF should match (HSEL=1)
 
   assign match = (HADDR ~^ Base) | Range;
-  assign HSEL = &match;
+  //assign HSEL = &match;
+  assign HSEL = (HADDR >= Base) && (HADDR <= Base + Range);
 
 endmodule
 
diff --git a/wally-pipelined/src/uncore/imem.sv b/wally-pipelined/src/uncore/imem.sv
index 86d23556..be42d0af 100644
--- a/wally-pipelined/src/uncore/imem.sv
+++ b/wally-pipelined/src/uncore/imem.sv
@@ -32,7 +32,8 @@ module imem (
   output logic             InstrAccessFaultF);
 
  /* verilator lint_off UNDRIVEN */
-  logic [`XLEN-1:0] RAM[0:65535];
+  logic [`XLEN-1:0] RAM[`TIMBASE>>(1+`XLEN/32):(`TIMRANGE-`TIMBASE)>>(1+`XLEN/32)];
+  logic [`XLEN-1:0] bootram[`BOOTTIMBASE>>(1+`XLEN/32):(`BOOTTIMRANGE-`BOOTTIMBASE)>>(1+`XLEN/32)];
  /* verilator lint_on UNDRIVEN */
   logic [15:0] adrbits;
   logic [`XLEN-1:0] rd;
@@ -43,13 +44,15 @@ module imem (
     else          assign adrbits = AdrF[18:3];
   endgenerate
 
-  assign #2 rd = RAM[adrbits]; // word aligned
+  //assign #2 rd = RAM[adrbits]; // word aligned
+  assign #2 rd = (AdrF < (`TIMBASE >> 1)) ? bootram[adrbits] : RAM[adrbits]; // busybear: 2 memory options
 
   // hack right now for unaligned 32-bit instructions
   // eventually this will need to cause a stall like a cache miss
   // when the instruction wraps around a cache line
   // could be optimized to only stall when the instruction wrapping is 32 bits
-  assign #2 rd2 = RAM[adrbits+1][15:0];
+  //assign #2 rd2 = RAM[adrbits+1][15:0];
+  assign #2 rd2 = (AdrF < (`TIMBASE >> 1)) ? bootram[adrbits+1][15:0] : RAM[adrbits+1][15:0]; //busybear: 2 memory options
   generate 
     if (`XLEN==32) begin
       assign InstrF = AdrF[1] ? {rd2[15:0], rd[31:16]} : rd;
@@ -61,11 +64,12 @@ module imem (
     end else begin
       assign InstrF = AdrF[2] ? (AdrF[1] ? {rd2[15:0], rd[63:48]} : rd[63:32])
                           : (AdrF[1] ? rd[47:16] : rd[31:0]);
-      if(`TIMBASE==0) begin
+      /*if(`TIMBASE==0) begin
         assign InstrAccessFaultF = 0;
       end else begin
         assign InstrAccessFaultF = (|AdrF[`XLEN-1:32]) | ~AdrF[31] | (|AdrF[30:16]); // memory mapped to 0x80000000-0x8000FFFF]
-      end
+      end*/
+      assign InstrAccessFaultF = 0; //busybear: for now, i know we're not doing this
     end
   endgenerate
 endmodule