From f201af4bb7720b0344fe256ea9cf0ce148b17790 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sun, 19 Dec 2021 11:49:15 -0800
Subject: [PATCH] Renamed zero to eq in flag generation

---
 wally-pipelined/src/ieu/comparator.sv | 6 +++---
 wally-pipelined/src/ieu/controller.sv | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/wally-pipelined/src/ieu/comparator.sv b/wally-pipelined/src/ieu/comparator.sv
index 14117274..0c161d6d 100644
--- a/wally-pipelined/src/ieu/comparator.sv
+++ b/wally-pipelined/src/ieu/comparator.sv
@@ -30,7 +30,7 @@ module comparator #(parameter WIDTH=32) (
   output logic [2:0]       flags);
 
   logic [WIDTH-1:0] bbar, diff;
-  logic             carry, zero, neg, overflow, lt, ltu;
+  logic             carry, eq, neg, overflow, lt, ltu;
 
   // NOTE: This can be replaced by some faster logic optimized
   // to just compute flags and not the difference.
@@ -40,13 +40,13 @@ module comparator #(parameter WIDTH=32) (
   assign {carry, diff} = a + bbar + 1;
 
   // condition code flags based on add/subtract output
-  assign zero = (diff == 0);
+  assign eq = (diff == 0);
   assign neg  = diff[WIDTH-1];
   // overflow occurs when the numbers being subtracted have the opposite sign 
   // and the result has the opposite sign fron the first
   assign overflow = (a[WIDTH-1] ^ b[WIDTH-1]) & (a[WIDTH-1] ^ diff[WIDTH-1]);
   assign lt = neg ^ overflow;
   assign ltu = ~carry;
-  assign flags = {zero, lt, ltu};
+  assign flags = {eq, lt, ltu};
 endmodule
 
diff --git a/wally-pipelined/src/ieu/controller.sv b/wally-pipelined/src/ieu/controller.sv
index 94f3d65c..b081d40f 100644
--- a/wally-pipelined/src/ieu/controller.sv
+++ b/wally-pipelined/src/ieu/controller.sv
@@ -97,7 +97,7 @@ module controller(
   logic        SubArithD;
   logic        subD, sraD, sltD, sltuD;
   logic        BranchTakenE;
-  logic        zeroE, ltE, ltuE;
+  logic        eqE, ltE, ltuE;
   logic        unused;
 	logic        BranchFlagE;
   logic        IEURegWriteE;
@@ -202,8 +202,8 @@ module controller(
                            {IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, MulDivE, AtomicE, InvalidateICacheE, FlushDCacheE, InstrValidE});
 
   // Branch Logic
-  assign {zeroE, ltE, ltuE} = FlagsE;
-  mux4 #(1) branchflagmux(zeroE, 1'b0, ltE, ltuE, Funct3E[2:1], BranchFlagE);
+  assign {eqE, ltE, ltuE} = FlagsE;
+  mux4 #(1) branchflagmux(eqE, 1'b0, ltE, ltuE, Funct3E[2:1], BranchFlagE);
   assign BranchTakenE = BranchFlagE ^ Funct3E[0];
     
   assign PCSrcE = JumpE | BranchE & BranchTakenE;