diff --git a/pipelined/regression/wally-pipelined.do b/pipelined/regression/wally-pipelined.do
index e0096dc9..0dadea94 100644
--- a/pipelined/regression/wally-pipelined.do
+++ b/pipelined/regression/wally-pipelined.do
@@ -34,7 +34,7 @@ vlib work
 if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
     vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
     # start and run simulation
-    vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt 
+    vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G DEBUG_TRACE=1 -o testbenchopt 
     vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829
 
     #-- Run the Simulation
@@ -48,7 +48,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
 } elseif {$2 eq "buildroot-no-trace"} {
     vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
     # start and run simulation
-    vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_SPOOFING=1 -o testbenchopt 
+    vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_IE_MTIME_CHECKPOINT=1 -G DEBUG_TRACE=0 -o testbenchopt 
     vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829
 
     #-- Run the Simulation
diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv
index 248e74c2..31add80a 100644
--- a/pipelined/testbench/testbench-linux.sv
+++ b/pipelined/testbench/testbench-linux.sv
@@ -27,15 +27,6 @@
 
 `include "wally-config.vh"
 
-`define DEBUG_TRACE 0
-// Debug Levels
-// 0: don't check against QEMU
-// 1: print disagreements with QEMU, but only halt on PCW disagreements
-// 2: halt on any disagreement with QEMU except CSRs
-// 3: halt on all disagreements with QEMU
-// 4: print memory accesses whenever they happen
-// 5: print everything
-
 module testbench;
   ///////////////////////////////////////////////////////////////////////////////
   /////////////////////////////////// CONFIG ////////////////////////////////////
@@ -46,6 +37,16 @@ module testbench;
   parameter CHECKPOINT   = 0;
   parameter RISCV_DIR = "/opt/riscv";
   parameter NO_SPOOFING = 0;
+  parameter DEBUG_TRACE = 0;
+  // Debug Levels
+  // 0: don't check against QEMU
+  // 1: print disagreements with QEMU, but only halt on PCW disagreements
+  // 2: halt on any disagreement with QEMU except CSRs
+  // 3: halt on all disagreements with QEMU
+  // 4: print memory accesses whenever they happen
+  // 5: print everything
+
+
 
 
 
@@ -479,7 +480,7 @@ module testbench;
     if (checkInstrM) begin \
       // read 1 line of the trace file \
       matchCount``STAGE = $fgets(line``STAGE, traceFile``STAGE); \
-      if(`DEBUG_TRACE >= 5) $display("Time %t, line %x", $time, line``STAGE); \
+      if(DEBUG_TRACE >= 5) $display("Time %t, line %x", $time, line``STAGE); \
       // extract PC, Instr \
       matchCount``STAGE = $sscanf(line``STAGE, "%x %x %s", ExpectedPC``STAGE, ExpectedInstr``STAGE, text``STAGE); \
       if (`"STAGE`"=="M") begin \
@@ -563,14 +564,14 @@ module testbench;
   `define checkEQ(NAME, VAL, EXPECTED) \
     if(VAL != EXPECTED) begin \
       $display("%tns, %d instrs: %s %x differs from expected %x", $time, AttemptedInstructionCount, NAME, VAL, EXPECTED); \
-      if ((NAME == "PCW") | (`DEBUG_TRACE >= 2)) fault = 1; \
+      if ((NAME == "PCW") | (DEBUG_TRACE >= 2)) fault = 1; \
     end
 
   `define checkCSR(CSR) \
     begin \
       if (CSR != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin \
         $display("%tns, %d instrs: CSR %s = %016x, does not equal expected value %016x", $time, AttemptedInstructionCount, ExpectedCSRArrayW[NumCSRPostWIndex], CSR, ExpectedCSRArrayValueW[NumCSRPostWIndex]); \
-        if(`DEBUG_TRACE >= 3) fault = 1; \
+        if(DEBUG_TRACE >= 3) fault = 1; \
       end \
     end
 
@@ -655,13 +656,13 @@ module testbench;
       // end sim
       if ((AttemptedInstructionCount == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $stop; $stop; end
       fault = 0;
-      if (`DEBUG_TRACE >= 1) begin
+      if (DEBUG_TRACE >= 1) begin
         `checkEQ("PCW",PCW,ExpectedPCW)
         //`checkEQ("InstrW",InstrW,ExpectedInstrW) <-- not viable because of
         // compressed to uncompressed conversion
         `checkEQ("Instr Count",dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2],InstrCountW)
         #2; // delay 2 ns.
-        if(`DEBUG_TRACE >= 5) begin
+        if(DEBUG_TRACE >= 5) begin
           $display("%tns, %d instrs: Reg Write Address %02d ? expected value: %02d", $time, AttemptedInstructionCount, dut.core.ieu.dp.regf.a3, ExpectedRegAdrW);
           $display("%tns, %d instrs: RF[%02d] %016x ? expected value: %016x", $time, AttemptedInstructionCount, ExpectedRegAdrW, dut.core.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW);
         end
@@ -671,13 +672,13 @@ module testbench;
           `checkEQ(name, dut.core.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW)
         end
         if (MemOpW.substr(0,2) == "Mem") begin
-          if(`DEBUG_TRACE >= 4) $display("\tIEUAdrW: %016x ? expected: %016x", IEUAdrW, ExpectedIEUAdrW);
+          if(DEBUG_TRACE >= 4) $display("\tIEUAdrW: %016x ? expected: %016x", IEUAdrW, ExpectedIEUAdrW);
           `checkEQ("IEUAdrW",IEUAdrW,ExpectedIEUAdrW)
           if(MemOpW == "MemR" | MemOpW == "MemRW") begin
-            if(`DEBUG_TRACE >= 4) $display("\tReadDataW: %016x ? expected: %016x", dut.core.ieu.dp.ReadDataW, ExpectedMemReadDataW);
+            if(DEBUG_TRACE >= 4) $display("\tReadDataW: %016x ? expected: %016x", dut.core.ieu.dp.ReadDataW, ExpectedMemReadDataW);
             `checkEQ("ReadDataW",dut.core.ieu.dp.ReadDataW,ExpectedMemReadDataW)
           end else if(MemOpW == "MemW" | MemOpW == "MemRW") begin
-            if(`DEBUG_TRACE >= 4) $display("\tWriteDataW: %016x ? expected: %016x", WriteDataW, ExpectedMemWriteDataW);
+            if(DEBUG_TRACE >= 4) $display("\tWriteDataW: %016x ? expected: %016x", WriteDataW, ExpectedMemWriteDataW);
             `checkEQ("WriteDataW",ExpectedMemWriteDataW,ExpectedMemWriteDataW)
           end
         end
@@ -717,7 +718,7 @@ module testbench;
           $display("processed %0d instructions with %0d warnings", AttemptedInstructionCount, warningCount);
           $stop; $stop;
         end
-      end // if (`DEBUG_TRACE >= 1)
+      end // if (DEBUG_TRACE >= 1)
     end // if (checkInstrW)
   end // always @ (negedge clk)