diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally
index 456ba8fe..48dd7c26 100755
--- a/pipelined/regression/regression-wally
+++ b/pipelined/regression/regression-wally
@@ -91,7 +91,7 @@ for test in tests32ic:
         grepstr="All tests ran without failures")
   configs.append(tc)
 
-tests32i = ["wally32periph"] 
+tests32i = ["arch32i", "wally32periph"] 
 for test in tests32i:
   tc = TestCase(
         name=test,
diff --git a/pipelined/src/fpu/postproc/divshiftcalc.sv b/pipelined/src/fpu/postproc/divshiftcalc.sv
index ee8581a5..8e36ad88 100644
--- a/pipelined/src/fpu/postproc/divshiftcalc.sv
+++ b/pipelined/src/fpu/postproc/divshiftcalc.sv
@@ -77,5 +77,5 @@ module divshiftcalc(
     // *** explain why radix 4 division needs a left shift by 1
     // *** can this shift be moved into the shiftcorrection logic?
     assign PreDivShiftIn = {{`NF{1'b0}}, DivQm, {`NORMSHIFTSZ-`DIVb+1-`NF{1'b0}}};
-    assign DivShiftIn = PreDivShiftIn << (`RADIX==4 & ~Sqrt); // {{`NF{1'b0}}, DivQm[`DIVb-1:0], {`NORMSHIFTSZ-`DIVb+2-`NF{1'b0}}};
+    assign DivShiftIn = PreDivShiftIn << (`RADIX==4 & ~Sqrt); 
 endmodule
diff --git a/pipelined/src/ieu/controller.sv b/pipelined/src/ieu/controller.sv
index d0b1e5fc..ab623b0e 100644
--- a/pipelined/src/ieu/controller.sv
+++ b/pipelined/src/ieu/controller.sv
@@ -236,5 +236,7 @@ module controller(
   // Stall pipeline at Fetch if a CSR Write or Fence is pending in the subsequent stages
   assign CSRWriteFencePendingDEM = CSRWriteD | CSRWriteE | CSRWriteM | FencePendingD | FencePendingE | FencePendingM;
 
-  assign StoreStallD = MemRWE[0] & ((|MemRWD) | (|AtomicD));
+  // the synchronous DTIM cannot read immediately after write
+  // a cache cannot read or write immediately after a write
+  assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & `DCACHE)) | (|AtomicD));
 endmodule