From efe7e88258c8a6e19463bf5668aa002e75f4a624 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 13 Jan 2023 22:12:06 -0800 Subject: [PATCH] csr cleanup --- pipelined/src/privileged/csr.sv | 47 +++++++--- pipelined/src/privileged/csri.sv | 21 +++-- pipelined/src/privileged/csrs.sv | 117 +++++++++++-------------- pipelined/src/privileged/csru.sv | 91 +++++++++---------- pipelined/src/privileged/privdec.sv | 27 ++---- pipelined/testbench/testbench-linux.sv | 10 +-- 6 files changed, 154 insertions(+), 159 deletions(-) diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index fb1067c4..289e09ae 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -201,6 +201,7 @@ module csr #(parameter .CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM, .MExtInt, .SExtInt, .MTimerInt, .MSwInt, .MIP_REGW, .MIE_REGW, .MIP_REGW_writeable); + csrsr csrsr(.clk, .reset, .StallW, .WriteMSTATUSM, .WriteMSTATUSHM, .WriteSSTATUSM, .TrapM, .FRegWriteM, .NextPrivilegeModeM, .PrivilegeModeW, @@ -209,6 +210,7 @@ module csr #(parameter .STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TW, .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TVM, .STATUS_FS, .BigEndianM); + csrm csrm(.clk, .reset, .InstrValidNotFlushedM, .CSRMWriteM, .MTrapM, .CSRAdrM, .NextEPCM, .NextCauseM, .NextMtvalM, .MSTATUS_REGW, .MSTATUSH_REGW, @@ -217,18 +219,39 @@ module csr #(parameter .MEDELEG_REGW, .MIDELEG_REGW,.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .MIP_REGW, .MIE_REGW, .WriteMSTATUSM, .WriteMSTATUSHM, .IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM); - csrs csrs(.clk, .reset, .InstrValidNotFlushedM, - .CSRSWriteM, .STrapM, .CSRAdrM, - .NextEPCM, .NextCauseM, .NextMtvalM, .SSTATUS_REGW, - .STATUS_TVM, .CSRWriteValM, .PrivilegeModeW, - .CSRSReadValM, .STVEC_REGW, .SEPC_REGW, - .SCOUNTEREN_REGW, - .SATP_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, - .WriteSSTATUSM, .IllegalCSRSAccessM); - csru csru(.clk, .reset, .InstrValidNotFlushedM, - .CSRUWriteM, .CSRAdrM, .CSRWriteValM, .STATUS_FS, .CSRUReadValM, - .SetFflagsM, .FRM_REGW, .WriteFRMM, .WriteFFLAGSM, - .IllegalCSRUAccessM); + + + if (`S_SUPPORTED) begin:csrs + csrs csrs(.clk, .reset, .InstrValidNotFlushedM, + .CSRSWriteM, .STrapM, .CSRAdrM, + .NextEPCM, .NextCauseM, .NextMtvalM, .SSTATUS_REGW, + .STATUS_TVM, .CSRWriteValM, .PrivilegeModeW, + .CSRSReadValM, .STVEC_REGW, .SEPC_REGW, + .SCOUNTEREN_REGW, + .SATP_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, + .WriteSSTATUSM, .IllegalCSRSAccessM); + end else begin + assign WriteSSTATUSM = 0; + assign CSRSReadValM = 0; + assign SEPC_REGW = 0; + assign STVEC_REGW = 0; + assign SCOUNTEREN_REGW = 0; + assign SATP_REGW = 0; + assign IllegalCSRSAccessM = 1; + end + + // Floating Point CSRs in User Mode only needed if Floating Point is supported + if (`F_SUPPORTED | `D_SUPPORTED) begin:csru + csru csru(.clk, .reset, .InstrValidNotFlushedM, + .CSRUWriteM, .CSRAdrM, .CSRWriteValM, .STATUS_FS, .CSRUReadValM, + .SetFflagsM, .FRM_REGW, .WriteFRMM, .WriteFFLAGSM, + .IllegalCSRUAccessM); + end else begin + assign FRM_REGW = 0; + assign CSRUReadValM = 0; + assign IllegalCSRUAccessM = 1; + end + if (`ZICOUNTERS_SUPPORTED) begin:counters csrc counters(.clk, .reset, .StallE, .StallM, .FlushM, .InstrValidNotFlushedM, .LoadStallD, .CSRMWriteM, diff --git a/pipelined/src/privileged/csri.sv b/pipelined/src/privileged/csri.sv index 751362f6..1e68f15f 100644 --- a/pipelined/src/privileged/csri.sv +++ b/pipelined/src/privileged/csri.sv @@ -33,20 +33,19 @@ module csri #(parameter MIE = 12'h304, MIP = 12'h344, SIE = 12'h104, - SIP = 12'h144 -) ( - input logic clk, reset, - input logic InstrValidNotFlushedM, - input logic CSRMWriteM, CSRSWriteM, - input logic [`XLEN-1:0] CSRWriteValM, - input logic [11:0] CSRAdrM, - (* mark_debug = "true" *) input logic MExtInt, SExtInt, MTimerInt, MSwInt, - output logic [11:0] MIP_REGW, MIE_REGW, + SIP = 12'h144) ( + input logic clk, reset, + input logic InstrValidNotFlushedM, + input logic CSRMWriteM, CSRSWriteM, + input logic [`XLEN-1:0] CSRWriteValM, + input logic [11:0] CSRAdrM, + (* mark_debug = "true" *) input logic MExtInt, SExtInt, MTimerInt, MSwInt, + output logic [11:0] MIP_REGW, MIE_REGW, (* mark_debug = "true" *) output logic [11:0] MIP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0 ); - logic [11:0] MIP_WRITE_MASK, SIP_WRITE_MASK, MIE_WRITE_MASK; - logic WriteMIPM, WriteMIEM, WriteSIPM, WriteSIEM; + logic [11:0] MIP_WRITE_MASK, SIP_WRITE_MASK, MIE_WRITE_MASK; + logic WriteMIPM, WriteMIEM, WriteSIPM, WriteSIEM; // Interrupt Write Enables assign WriteMIPM = CSRMWriteM & (CSRAdrM == MIP) & InstrValidNotFlushedM; diff --git a/pipelined/src/privileged/csrs.sv b/pipelined/src/privileged/csrs.sv index 7c67d09a..438aca97 100644 --- a/pipelined/src/privileged/csrs.sv +++ b/pipelined/src/privileged/csrs.sv @@ -41,11 +41,7 @@ module csrs #(parameter SCAUSE = 12'h142, STVAL = 12'h143, SIP= 12'h144, - SATP = 12'h180, - // Constants - ZERO = {(`XLEN){1'b0}}, - SEDELEG_MASK = ~(ZERO | `XLEN'b111 << 9) - ) ( + SATP = 12'h180) ( input logic clk, reset, input logic InstrValidNotFlushedM, input logic CSRSWriteM, STrapM, @@ -63,67 +59,60 @@ module csrs #(parameter output logic IllegalCSRSAccessM ); + // Constants + localparam ZERO = {(`XLEN){1'b0}}; + localparam SEDELEG_MASK = ~(ZERO | `XLEN'b111 << 9); - // Supervisor mode CSRs sometimes supported - if (`S_SUPPORTED) begin:csrs - logic WriteSTVECM; - logic WriteSSCRATCHM, WriteSEPCM; - logic WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM; - (* mark_debug = "true" *) logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW; - (* mark_debug = "true" *) logic [`XLEN-1:0] SCAUSE_REGW; - - assign WriteSSTATUSM = CSRSWriteM & (CSRAdrM == SSTATUS) & InstrValidNotFlushedM; - assign WriteSTVECM = CSRSWriteM & (CSRAdrM == STVEC) & InstrValidNotFlushedM; - assign WriteSSCRATCHM = CSRSWriteM & (CSRAdrM == SSCRATCH) & InstrValidNotFlushedM; - assign WriteSEPCM = STrapM | (CSRSWriteM & (CSRAdrM == SEPC)) & InstrValidNotFlushedM; - assign WriteSCAUSEM = STrapM | (CSRSWriteM & (CSRAdrM == SCAUSE)) & InstrValidNotFlushedM; - assign WriteSTVALM = STrapM | (CSRSWriteM & (CSRAdrM == STVAL)) & InstrValidNotFlushedM; - assign WriteSATPM = CSRSWriteM & (CSRAdrM == SATP) & (PrivilegeModeW == `M_MODE | ~STATUS_TVM) & InstrValidNotFlushedM; - assign WriteSCOUNTERENM = CSRSWriteM & (CSRAdrM == SCOUNTEREN) & InstrValidNotFlushedM; + logic WriteSTVECM; + logic WriteSSCRATCHM, WriteSEPCM; + logic WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM; + (* mark_debug = "true" *) logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW; + (* mark_debug = "true" *) logic [`XLEN-1:0] SCAUSE_REGW; + + // write enables + assign WriteSSTATUSM = CSRSWriteM & (CSRAdrM == SSTATUS) & InstrValidNotFlushedM; + assign WriteSTVECM = CSRSWriteM & (CSRAdrM == STVEC) & InstrValidNotFlushedM; + assign WriteSSCRATCHM = CSRSWriteM & (CSRAdrM == SSCRATCH) & InstrValidNotFlushedM; + assign WriteSEPCM = STrapM | (CSRSWriteM & (CSRAdrM == SEPC)) & InstrValidNotFlushedM; + assign WriteSCAUSEM = STrapM | (CSRSWriteM & (CSRAdrM == SCAUSE)) & InstrValidNotFlushedM; + assign WriteSTVALM = STrapM | (CSRSWriteM & (CSRAdrM == STVAL)) & InstrValidNotFlushedM; + assign WriteSATPM = CSRSWriteM & (CSRAdrM == SATP) & (PrivilegeModeW == `M_MODE | ~STATUS_TVM) & InstrValidNotFlushedM; + assign WriteSCOUNTERENM = CSRSWriteM & (CSRAdrM == SCOUNTEREN) & InstrValidNotFlushedM; - // CSRs - flopenr #(`XLEN) STVECreg(clk, reset, WriteSTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, STVEC_REGW); - flopenr #(`XLEN) SSCRATCHreg(clk, reset, WriteSSCRATCHM, CSRWriteValM, SSCRATCH_REGW); - flopenr #(`XLEN) SEPCreg(clk, reset, WriteSEPCM, NextEPCM, SEPC_REGW); - flopenr #(`XLEN) SCAUSEreg(clk, reset, WriteSCAUSEM, NextCauseM, SCAUSE_REGW); - flopenr #(`XLEN) STVALreg(clk, reset, WriteSTVALM, NextMtvalM, STVAL_REGW); - if (`VIRTMEM_SUPPORTED) - flopenr #(`XLEN) SATPreg(clk, reset, WriteSATPM, CSRWriteValM, SATP_REGW); - else - assign SATP_REGW = 0; // hardwire to zero if virtual memory not supported - flopens #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], SCOUNTEREN_REGW); + // CSRs + flopenr #(`XLEN) STVECreg(clk, reset, WriteSTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, STVEC_REGW); + flopenr #(`XLEN) SSCRATCHreg(clk, reset, WriteSSCRATCHM, CSRWriteValM, SSCRATCH_REGW); + flopenr #(`XLEN) SEPCreg(clk, reset, WriteSEPCM, NextEPCM, SEPC_REGW); + flopenr #(`XLEN) SCAUSEreg(clk, reset, WriteSCAUSEM, NextCauseM, SCAUSE_REGW); + flopenr #(`XLEN) STVALreg(clk, reset, WriteSTVALM, NextMtvalM, STVAL_REGW); + if (`VIRTMEM_SUPPORTED) + flopenr #(`XLEN) SATPreg(clk, reset, WriteSATPM, CSRWriteValM, SATP_REGW); + else + assign SATP_REGW = 0; // hardwire to zero if virtual memory not supported + flopens #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], SCOUNTEREN_REGW); - // CSR Reads - always_comb begin:csrr - IllegalCSRSAccessM = 0; - case (CSRAdrM) - SSTATUS: CSRSReadValM = SSTATUS_REGW; - STVEC: CSRSReadValM = STVEC_REGW; - SIP: CSRSReadValM = {{(`XLEN-12){1'b0}}, MIP_REGW & 12'h222 & MIDELEG_REGW}; // only read supervisor fields - SIE: CSRSReadValM = {{(`XLEN-12){1'b0}}, MIE_REGW & 12'h222}; // only read supervisor fields - SSCRATCH: CSRSReadValM = SSCRATCH_REGW; - SEPC: CSRSReadValM = SEPC_REGW; - SCAUSE: CSRSReadValM = SCAUSE_REGW; - STVAL: CSRSReadValM = STVAL_REGW; - SATP: if (`VIRTMEM_SUPPORTED & (PrivilegeModeW == `M_MODE | ~STATUS_TVM)) CSRSReadValM = SATP_REGW; - else begin - CSRSReadValM = 0; - if (PrivilegeModeW == `S_MODE & STATUS_TVM) IllegalCSRSAccessM = 1; - end - SCOUNTEREN:CSRSReadValM = {{(`XLEN-32){1'b0}}, SCOUNTEREN_REGW}; - default: begin - CSRSReadValM = 0; - IllegalCSRSAccessM = 1; - end - endcase - end - end else begin - assign WriteSSTATUSM = 0; - assign CSRSReadValM = 0; - assign SEPC_REGW = 0; - assign STVEC_REGW = 0; - assign SCOUNTEREN_REGW = 0; - assign SATP_REGW = 0; - assign IllegalCSRSAccessM = 1; + // CSR Reads + always_comb begin:csrr + IllegalCSRSAccessM = 0; + case (CSRAdrM) + SSTATUS: CSRSReadValM = SSTATUS_REGW; + STVEC: CSRSReadValM = STVEC_REGW; + SIP: CSRSReadValM = {{(`XLEN-12){1'b0}}, MIP_REGW & 12'h222 & MIDELEG_REGW}; // only read supervisor fields + SIE: CSRSReadValM = {{(`XLEN-12){1'b0}}, MIE_REGW & 12'h222}; // only read supervisor fields + SSCRATCH: CSRSReadValM = SSCRATCH_REGW; + SEPC: CSRSReadValM = SEPC_REGW; + SCAUSE: CSRSReadValM = SCAUSE_REGW; + STVAL: CSRSReadValM = STVAL_REGW; + SATP: if (`VIRTMEM_SUPPORTED & (PrivilegeModeW == `M_MODE | ~STATUS_TVM)) CSRSReadValM = SATP_REGW; + else begin + CSRSReadValM = 0; + if (PrivilegeModeW == `S_MODE & STATUS_TVM) IllegalCSRSAccessM = 1; + end + SCOUNTEREN:CSRSReadValM = {{(`XLEN-32){1'b0}}, SCOUNTEREN_REGW}; + default: begin + CSRSReadValM = 0; + IllegalCSRSAccessM = 1; + end + endcase end endmodule diff --git a/pipelined/src/privileged/csru.sv b/pipelined/src/privileged/csru.sv index a5f6c5ee..08e2035d 100644 --- a/pipelined/src/privileged/csru.sv +++ b/pipelined/src/privileged/csru.sv @@ -32,59 +32,52 @@ module csru #(parameter FFLAGS = 12'h001, FRM = 12'h002, FCSR = 12'h003) ( - input logic clk, reset, - input logic InstrValidNotFlushedM, - input logic CSRUWriteM, - input logic [11:0] CSRAdrM, - input logic [`XLEN-1:0] CSRWriteValM, - input logic [1:0] STATUS_FS, - output logic [`XLEN-1:0] CSRUReadValM, - input logic [4:0] SetFflagsM, - output logic [2:0] FRM_REGW, - output logic WriteFRMM, WriteFFLAGSM, - output logic IllegalCSRUAccessM + input logic clk, reset, + input logic InstrValidNotFlushedM, + input logic CSRUWriteM, + input logic [11:0] CSRAdrM, + input logic [`XLEN-1:0] CSRWriteValM, + input logic [1:0] STATUS_FS, + output logic [`XLEN-1:0] CSRUReadValM, + input logic [4:0] SetFflagsM, + output logic [2:0] FRM_REGW, + output logic WriteFRMM, WriteFFLAGSM, + output logic IllegalCSRUAccessM ); - // Floating Point CSRs in User Mode only needed if Floating Point is supported - if (`F_SUPPORTED | `D_SUPPORTED) begin:csru - logic [4:0] FFLAGS_REGW; - logic [2:0] NextFRMM; - logic [4:0] NextFFLAGSM; - - // Write enables - //assign WriteFCSRM = CSRUWriteM & (CSRAdrM == FCSR) & InstrValidNotFlushedM; - assign WriteFRMM = (CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FRM | CSRAdrM == FCSR)) & InstrValidNotFlushedM; - assign WriteFFLAGSM = (CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FFLAGS | CSRAdrM == FCSR)) & InstrValidNotFlushedM; - - // Write Values - assign NextFRMM = (CSRAdrM == FCSR) ? CSRWriteValM[7:5] : CSRWriteValM[2:0]; - assign NextFFLAGSM = WriteFFLAGSM ? CSRWriteValM[4:0] : FFLAGS_REGW | SetFflagsM; + logic [4:0] FFLAGS_REGW; + logic [2:0] NextFRMM; + logic [4:0] NextFFLAGSM; + + // Write enables + //assign WriteFCSRM = CSRUWriteM & (CSRAdrM == FCSR) & InstrValidNotFlushedM; + assign WriteFRMM = (CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FRM | CSRAdrM == FCSR)) & InstrValidNotFlushedM; + assign WriteFFLAGSM = (CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FFLAGS | CSRAdrM == FCSR)) & InstrValidNotFlushedM; - // CSRs - flopenr #(3) FRMreg(clk, reset, WriteFRMM, NextFRMM, FRM_REGW); - flopr #(5) FFLAGSreg(clk, reset, NextFFLAGSM, FFLAGS_REGW); + // Write Values + assign NextFRMM = (CSRAdrM == FCSR) ? CSRWriteValM[7:5] : CSRWriteValM[2:0]; + assign NextFFLAGSM = WriteFFLAGSM ? CSRWriteValM[4:0] : FFLAGS_REGW | SetFflagsM; - // CSR Reads - always_comb begin - if (STATUS_FS == 2'b00) begin // fpu disabled, trap - IllegalCSRUAccessM = 1; - CSRUReadValM = 0; - end else begin - IllegalCSRUAccessM = 0; - case (CSRAdrM) - FFLAGS: CSRUReadValM = {{(`XLEN-5){1'b0}}, FFLAGS_REGW}; - FRM: CSRUReadValM = {{(`XLEN-3){1'b0}}, FRM_REGW}; - FCSR: CSRUReadValM = {{(`XLEN-8){1'b0}}, FRM_REGW, FFLAGS_REGW}; - default: begin - CSRUReadValM = 0; - IllegalCSRUAccessM = 1; - end - endcase - end + // CSRs + flopenr #(3) FRMreg(clk, reset, WriteFRMM, NextFRMM, FRM_REGW); + flopr #(5) FFLAGSreg(clk, reset, NextFFLAGSM, FFLAGS_REGW); + + // CSR Reads + always_comb begin + if (STATUS_FS == 2'b00) begin // fpu disabled, trap + IllegalCSRUAccessM = 1; + CSRUReadValM = 0; + end else begin + IllegalCSRUAccessM = 0; + case (CSRAdrM) + FFLAGS: CSRUReadValM = {{(`XLEN-5){1'b0}}, FFLAGS_REGW}; + FRM: CSRUReadValM = {{(`XLEN-3){1'b0}}, FRM_REGW}; + FCSR: CSRUReadValM = {{(`XLEN-8){1'b0}}, FRM_REGW, FFLAGS_REGW}; + default: begin + CSRUReadValM = 0; + IllegalCSRUAccessM = 1; + end + endcase end - end else begin // if not supported - assign FRM_REGW = 0; - assign CSRUReadValM = 0; - assign IllegalCSRUAccessM = 1; end endmodule diff --git a/pipelined/src/privileged/privdec.sv b/pipelined/src/privileged/privdec.sv index db6b33b8..fe73ebbf 100644 --- a/pipelined/src/privileged/privdec.sv +++ b/pipelined/src/privileged/privdec.sv @@ -41,18 +41,18 @@ module privdec ( input logic STATUS_TSR, STATUS_TVM, STATUS_TW, // status bits output logic IllegalInstrFaultM, // Illegal instruction output logic EcallFaultM, BreakpointFaultM, // Ecall or breakpoint; must retire, so don't flush it when the trap occurs - output logic sretM, mretM, - output logic wfiM, sfencevmaM + output logic sretM, mretM, // return instructions + output logic wfiM, sfencevmaM // wfi / sfence.fma instructions ); - logic IllegalPrivilegedInstrM; - logic WFITimeoutM; - logic StallMQ; - logic ebreakM, ecallM; + logic IllegalPrivilegedInstrM; // privileged instruction isn't a legal one or in legal mode + logic WFITimeoutM; // WFI reaches timeout threshold + logic ebreakM, ecallM; // ebreak / ecall instructions /////////////////////////////////////////// // Decode privileged instructions /////////////////////////////////////////// + assign sretM = PrivilegedM & (InstrM[31:20] == 12'b000100000010) & `S_SUPPORTED & (PrivilegeModeW == `M_MODE | PrivilegeModeW == `S_MODE & ~STATUS_TSR); assign mretM = PrivilegedM & (InstrM[31:20] == 12'b001100000010) & (PrivilegeModeW == `M_MODE); @@ -65,6 +65,7 @@ module privdec ( /////////////////////////////////////////// // WFI timeout Privileged Spec 3.1.6.5 /////////////////////////////////////////// + if (`U_SUPPORTED) begin:wfi logic [`WFI_TIMEOUT_BIT:0] WFICount, WFICountPlus1; assign WFICountPlus1 = WFICount + 1; @@ -75,24 +76,14 @@ module privdec ( /////////////////////////////////////////// // Extract exceptions by name and handle them /////////////////////////////////////////// + assign BreakpointFaultM = ebreakM; // could have other causes from a debugger assign EcallFaultM = ecallM; - /////////////////////////////////////////// - // sfence.vma causes TLB flushes - /////////////////////////////////////////// - // sets ITLBFlush to pulse for one cycle of the sfence.vma instruction - // In this instr we want to flush the tlb and then do a pagetable walk to update the itlb and continue the program. - // But we're still in the stalled sfence instruction, so if itlbflushf == sfencevmaM, tlbflush would never drop and - // the tlbwrite would never take place after the pagetable walk. by adding in ~StallMQ, we are able to drop itlbflush - // after a cycle AND pulse it for another cycle on any further back-to-back sfences. -// flopr #(1) StallMReg(.clk, .reset, .d(StallM), .q(StallMQ)); -// assign ITLBFlushF = sfencevmaM & ~StallMQ; -// assign DTLBFlushM = sfencevmaM; - /////////////////////////////////////////// // Fault on illegal instructions /////////////////////////////////////////// + assign IllegalPrivilegedInstrM = PrivilegedM & ~(sretM|mretM|ecallM|ebreakM|wfiM|sfencevmaM); assign IllegalInstrFaultM = (IllegalIEUInstrFaultM & IllegalFPUInstrM) | IllegalPrivilegedInstrM | IllegalCSRAccessM | WFITimeoutM; diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv index d7549ca2..d4034e0b 100644 --- a/pipelined/testbench/testbench-linux.sv +++ b/pipelined/testbench/testbench-linux.sv @@ -155,7 +155,7 @@ module testbench; `define MCOUNTEREN `CSR_BASE.csrm.mcounteren.MCOUNTERENreg.q `define SCOUNTEREN `CSR_BASE.csrs.csrs.SCOUNTERENreg.q `define MSCRATCH `CSR_BASE.csrm.MSCRATCHreg.q - `define SSCRATCH `CSR_BASE.csrs.csrs.SSCRATCHreg.q + `define SSCRATCH `CSR_BASE.csrs.csrs.csrs.SSCRATCHreg.q `define MTVEC `CSR_BASE.csrm.MTVECreg.q `define STVEC `CSR_BASE.csrs.csrs.STVECreg.q `define SATP `CSR_BASE.csrs.csrs.genblk1.SATPreg.q @@ -700,16 +700,16 @@ module testbench; case(ExpectedCSRArrayW[NumCSRPostWIndex]) "mhartid": `checkCSR(`CSR_BASE.csrm.MHARTID_REGW) "mstatus": `checkCSR(`CSR_BASE.csrm.MSTATUS_REGW) - "sstatus": `checkCSR(`CSR_BASE.csrs.SSTATUS_REGW) + "sstatus": `checkCSR(`CSR_BASE.csrs.csrs.SSTATUS_REGW) "mtvec": `checkCSR(`CSR_BASE.csrm.MTVEC_REGW) "mie": `checkCSR(`CSR_BASE.csrm.MIE_REGW) "mideleg": `checkCSR(`CSR_BASE.csrm.MIDELEG_REGW) "medeleg": `checkCSR(`CSR_BASE.csrm.MEDELEG_REGW) "mepc": `checkCSR(`CSR_BASE.csrm.MEPC_REGW) "mtval": `checkCSR(`CSR_BASE.csrm.MTVAL_REGW) - "sepc": `checkCSR(`CSR_BASE.csrs.SEPC_REGW) + "sepc": `checkCSR(`CSR_BASE.csrs.csrs.SEPC_REGW) "scause": `checkCSR(`CSR_BASE.csrs.csrs.SCAUSE_REGW) - "stvec": `checkCSR(`CSR_BASE.csrs.STVEC_REGW) + "stvec": `checkCSR(`CSR_BASE.csrs.csrs.STVEC_REGW) "stval": `checkCSR(`CSR_BASE.csrs.csrs.STVAL_REGW) "mip": begin `checkCSR(`CSR_BASE.csrm.MIP_REGW) @@ -738,7 +738,7 @@ module testbench; // New IP spoofing logic globalIntsBecomeEnabled; - assign globalIntsBecomeEnabled = (`CSR_BASE.csrm.WriteMSTATUSM || `CSR_BASE.csrs.WriteSSTATUSM) && (|(`CSR_BASE.CSRWriteValM & (~`CSR_BASE.csrm.MSTATUS_REGW) & 32'h22)); + assign globalIntsBecomeEnabled = (`CSR_BASE.csrm.WriteMSTATUSM || `CSR_BASE.csrs.csrs.WriteSSTATUSM) && (|(`CSR_BASE.CSRWriteValM & (~`CSR_BASE.csrm.MSTATUS_REGW) & 32'h22)); logic checkInterruptM; assign checkInterruptM = dut.core.ieu.InstrValidM & ~dut.core.priv.priv.trap.InstrPageFaultM & ~dut.core.priv.priv.trap.InterruptM;