From eceb41805637ebde60650065a0e74aad8172bddc Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 19 Dec 2021 17:57:12 -0600 Subject: [PATCH] Implemented what I think is the last required change for the lsu state machine. --- wally-pipelined/src/lsu/lsu.sv | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 669b5ee5..cff0a417 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -222,8 +222,8 @@ module lsu // signal to CPU it needs to wait on HPTW. assign InterlockStall_BUG = (CurrState == STATE_T0_READY & (DTLBMissM | ITLBMissF)) | - (CurrState == STATE_T3_DTLB_MISS & ~WalkerPageFaultM) | (CurrState == STATE_T4_ITLB_MISS & ~WalkerInstrPageFaultF) | - (CurrState == STATE_T5_ITLB_MISS & ~WalkerInstrPageFaultF) | (CurrState == STATE_T7_DITLB_MISS & ~WalkerPageFaultM); + (CurrState == STATE_T3_DTLB_MISS & ~WalkerPageFaultM) | (CurrState == STATE_T4_ITLB_MISS & ~WalkerInstrPageFaultRaw) | + (CurrState == STATE_T5_ITLB_MISS & ~WalkerInstrPageFaultRaw) | (CurrState == STATE_T7_DITLB_MISS & ~WalkerPageFaultM); assign InterlockStall = InterlockStall_BUG === 1'bx ? 1'b0 : InterlockStall_BUG; @@ -234,6 +234,7 @@ module lsu (CurrState == STATE_T5_ITLB_MISS) | (CurrState == STATE_T7_DITLB_MISS); assign IgnoreRequest = CurrState == STATE_T0_READY & (ITLBMissF | DTLBMissM); + assign WalkerInstrPageFaultF = WalkerInstrPageFaultRaw | CurrState == STATE_T0_FAULT_REPLAY; flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM); @@ -259,7 +260,7 @@ module lsu .HPTWStall, .AnyCPUReqM, .MemAfterIWalkDone, - .WalkerInstrPageFaultF(WalkerInstrPageFaultF), + .WalkerInstrPageFaultF(WalkerInstrPageFaultRaw), .WalkerLoadPageFaultM(WalkerLoadPageFaultM), .WalkerStorePageFaultM(WalkerStorePageFaultM));