diff --git a/src/mmu/adrdecs.sv b/src/mmu/adrdecs.sv
index 679bd185..b1832d8c 100644
--- a/src/mmu/adrdecs.sv
+++ b/src/mmu/adrdecs.sv
@@ -38,8 +38,8 @@ module adrdecs (
 
   localparam logic [3:0]          SUPPORTED_SIZE = (`LLEN == 32 ? 4'b0111 : 4'b1111);
  // Determine which region of physical memory (if any) is being accessed
-  adrdec dtimdec(PhysicalAddress, `DTIM_BASE, `DTIM_RANGE, `DTIM_SUPPORTED, AccessRWX, Size, SUPPORTED_SIZE, SelRegions[10]);  
-  adrdec iromdec(PhysicalAddress, `IROM_BASE, `IROM_RANGE, `IROM_SUPPORTED, AccessRWX, Size, SUPPORTED_SIZE, SelRegions[9]);  
+  adrdec dtimdec(PhysicalAddress, `DTIM_BASE, `DTIM_RANGE, `DTIM_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE, SelRegions[10]);  
+  adrdec iromdec(PhysicalAddress, `IROM_BASE, `IROM_RANGE, `IROM_SUPPORTED, AccessRX, Size, SUPPORTED_SIZE, SelRegions[9]);  
   adrdec ddr4dec(PhysicalAddress, `EXT_MEM_BASE, `EXT_MEM_RANGE, `EXT_MEM_SUPPORTED, AccessRWX, Size, SUPPORTED_SIZE, SelRegions[8]);  
   adrdec bootromdec(PhysicalAddress, `BOOTROM_BASE, `BOOTROM_RANGE, `BOOTROM_SUPPORTED, AccessRX, Size, SUPPORTED_SIZE, SelRegions[7]);
   adrdec uncoreramdec(PhysicalAddress, `UNCORE_RAM_BASE, `UNCORE_RAM_RANGE, `UNCORE_RAM_SUPPORTED, AccessRWX, Size, SUPPORTED_SIZE, SelRegions[6]);
diff --git a/src/mmu/pmachecker.sv b/src/mmu/pmachecker.sv
index e46cfe8b..909cc564 100644
--- a/src/mmu/pmachecker.sv
+++ b/src/mmu/pmachecker.sv
@@ -58,8 +58,12 @@ module pmachecker (
 
   // Only non-core RAM/ROM memory regions are cacheable
   assign Cacheable = SelRegions[8] | SelRegions[7] | SelRegions[6];
-  assign Idempotent = SelRegions[10] | SelRegions[9] | SelRegions[8] | SelRegions[6];
-  assign AtomicAllowed = SelRegions[10] | SelRegions[9] | SelRegions[8] | SelRegions[6];
+  // Nonidemdempotent means access could have side effect and must not be done speculatively or redundantly
+  // I/O is nonidempotent.  
+  assign Idempotent = SelRegions[10] | SelRegions[9] | SelRegions[8] | SelRegions[7] | SelRegions[6];
+  // Atomic operations are only allowed on RAM
+  assign AtomicAllowed = SelRegions[10] | SelRegions[8] | SelRegions[6];
+  // Check if tightly integrated memories are selected
   assign SelTIM = SelRegions[10] | SelRegions[9];
 
   // Detect access faults
diff --git a/synthDC/Makefile b/synthDC/Makefile
index 136e610d..d29c1133 100755
--- a/synthDC/Makefile
+++ b/synthDC/Makefile
@@ -12,7 +12,7 @@ export MOD ?= orig
 # title to add a note in the synth's directory name
 TITLE = 
 # tsmc28, sky130, and sky90 presently supported
-export TECH ?= tsmc28
+export TECH ?= sky90
 # MAXCORES allows parallel compilation, which is faster but less CPU-efficient
 # Avoid when doing sweeps of many optimization points in parallel
 export MAXCORES ?= 1