diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 3bae41c4..e8921999 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -71,22 +71,28 @@ create_debug_port u_ila_0 probe set_property port_width 6 [get_debug_ports u_ila_0/probe13] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[11]} ]] + + create_debug_port u_ila_0 probe -set_property port_width 5 [get_debug_ports u_ila_0/probe14] +set_property port_width 64 [get_debug_ports u_ila_0/probe14] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] -connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[0]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[1]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[2]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[3]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[4]} ]] +connect_debug_port u_ila_0/probe14 [get_nets [list {HRDATAEXT[0]} {HRDATAEXT[1]} {HRDATAEXT[2]} {HRDATAEXT[3]} {HRDATAEXT[4]} {HRDATAEXT[5]} {HRDATAEXT[6]} {HRDATAEXT[7]} {HRDATAEXT[8]} {HRDATAEXT[9]} {HRDATAEXT[10]} {HRDATAEXT[11]} {HRDATAEXT[12]} {HRDATAEXT[13]} {HRDATAEXT[14]} {HRDATAEXT[15]} {HRDATAEXT[16]} {HRDATAEXT[17]} {HRDATAEXT[18]} {HRDATAEXT[19]} {HRDATAEXT[20]} {HRDATAEXT[21]} {HRDATAEXT[22]} {HRDATAEXT[23]} {HRDATAEXT[24]} {HRDATAEXT[25]} {HRDATAEXT[26]} {HRDATAEXT[27]} {HRDATAEXT[28]} {HRDATAEXT[29]} {HRDATAEXT[30]} {HRDATAEXT[31]} {HRDATAEXT[32]} {HRDATAEXT[33]} {HRDATAEXT[34]} {HRDATAEXT[35]} {HRDATAEXT[36]} {HRDATAEXT[37]} {HRDATAEXT[38]} {HRDATAEXT[39]} {HRDATAEXT[40]} {HRDATAEXT[41]} {HRDATAEXT[42]} {HRDATAEXT[43]} {HRDATAEXT[44]} {HRDATAEXT[45]} {HRDATAEXT[46]} {HRDATAEXT[47]} {HRDATAEXT[48]} {HRDATAEXT[49]} {HRDATAEXT[50]} {HRDATAEXT[51]} {HRDATAEXT[52]} {HRDATAEXT[53]} {HRDATAEXT[54]} {HRDATAEXT[55]} {HRDATAEXT[56]} {HRDATAEXT[57]} {HRDATAEXT[58]} {HRDATAEXT[59]} {HRDATAEXT[60]} {HRDATAEXT[61]} {HRDATAEXT[62]} {HRDATAEXT[63]} ]] + create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe15] +set_property port_width 1 [get_debug_ports u_ila_0/probe15] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] -connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_ERROR_CODE_Q[0]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_ERROR_CODE_Q[1]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_ERROR_CODE_Q[2]} ]] +connect_debug_port u_ila_0/probe15 [get_nets [list {HREADYEXT} ]] + create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe16] +set_property port_width 1 [get_debug_ports u_ila_0/probe16] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] -connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/r_DAT_Q[0]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/r_DAT_Q[1]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/r_DAT_Q[2]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/r_DAT_Q[3]} ]] +connect_debug_port u_ila_0/probe16 [get_nets [list {HRESPEXT} ]] + create_debug_port u_ila_0 probe set_property port_width 4 [get_debug_ports u_ila_0/probe17] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17] connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[0]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[1]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[2]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[3]} ]] + create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe18] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18] @@ -118,18 +124,22 @@ set_property port_width 63 [get_debug_ports u_ila_0/probe23] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23] connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[63]} ]] + create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe24] +set_property port_width 1 [get_debug_ports u_ila_0/probe24] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24] -connect_debug_port u_ila_0/probe24 [get_nets [list {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[0]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[1]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[2]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[3]} ]] +connect_debug_port u_ila_0/probe24 [get_nets [list {HSELEXT} ]] + create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe25] +set_property port_width 32 [get_debug_ports u_ila_0/probe25] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25] -connect_debug_port u_ila_0/probe25 [get_nets [list {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/i_SD_DAT[0]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/i_SD_DAT[1]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/i_SD_DAT[2]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/i_SD_DAT[3]} ]] +connect_debug_port u_ila_0/probe25 [get_nets [list {HADDR[0]} {HADDR[1]} {HADDR[2]} {HADDR[3]} {HADDR[4]} {HADDR[5]} {HADDR[6]} {HADDR[7]} {HADDR[8]} {HADDR[9]} {HADDR[10]} {HADDR[11]} {HADDR[12]} {HADDR[13]} {HADDR[14]} {HADDR[15]} {HADDR[16]} {HADDR[17]} {HADDR[18]} {HADDR[19]} {HADDR[20]} {HADDR[21]} {HADDR[22]} {HADDR[23]} {HADDR[24]} {HADDR[25]} {HADDR[26]} {HADDR[27]} {HADDR[28]} {HADDR[29]} {HADDR[30]} {HADDR[31]} ]] + create_debug_port u_ila_0 probe -set_property port_width 12 [get_debug_ports u_ila_0/probe26] +set_property port_width 64 [get_debug_ports u_ila_0/probe26] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26] -connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[0]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[1]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[2]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[3]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[4]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[5]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[6]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[7]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[8]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[9]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[10]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[11]} ]] +connect_debug_port u_ila_0/probe26 [get_nets [list {HWDATA[0]} {HWDATA[1]} {HWDATA[2]} {HWDATA[3]} {HWDATA[4]} {HWDATA[5]} {HWDATA[6]} {HWDATA[7]} {HWDATA[8]} {HWDATA[9]} {HWDATA[10]} {HWDATA[11]} {HWDATA[12]} {HWDATA[13]} {HWDATA[14]} {HWDATA[15]} {HWDATA[16]} {HWDATA[17]} {HWDATA[18]} {HWDATA[19]} {HWDATA[20]} {HWDATA[21]} {HWDATA[22]} {HWDATA[23]} {HWDATA[24]} {HWDATA[25]} {HWDATA[26]} {HWDATA[27]} {HWDATA[28]} {HWDATA[29]} {HWDATA[30]} {HWDATA[31]} {HWDATA[32]} {HWDATA[33]} {HWDATA[34]} {HWDATA[35]} {HWDATA[36]} {HWDATA[37]} {HWDATA[38]} {HWDATA[39]} {HWDATA[40]} {HWDATA[41]} {HWDATA[42]} {HWDATA[43]} {HWDATA[44]} {HWDATA[45]} {HWDATA[46]} {HWDATA[47]} {HWDATA[48]} {HWDATA[49]} {HWDATA[50]} {HWDATA[51]} {HWDATA[52]} {HWDATA[53]} {HWDATA[54]} {HWDATA[55]} {HWDATA[56]} {HWDATA[57]} {HWDATA[58]} {HWDATA[59]} {HWDATA[60]} {HWDATA[61]} {HWDATA[62]} {HWDATA[63]} ]] + create_debug_port u_ila_0 probe set_property port_width 4 [get_debug_ports u_ila_0/probe27] @@ -140,14 +150,18 @@ create_debug_port u_ila_0 probe set_property port_width 6 [get_debug_ports u_ila_0/probe28] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28] connect_debug_port u_ila_0/probe28 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[1]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[3]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[7]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[9]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[11]} ]] + + create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe29] +set_property port_width 1 [get_debug_ports u_ila_0/probe29] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29] -connect_debug_port u_ila_0/probe29 [get_nets [list {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/r_IC_OUT[0]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/r_IC_OUT[1]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/r_IC_OUT[2]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/r_IC_OUT[3]} ]] +connect_debug_port u_ila_0/probe29 [get_nets [list {HWRITE} ]] + create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe30] +set_property port_width 3 [get_debug_ports u_ila_0/probe30] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30] -connect_debug_port u_ila_0/probe30 [get_nets [list {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[0]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[1]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[2]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[3]} ]] +connect_debug_port u_ila_0/probe30 [get_nets [list {HSIZE[0]} {HSIZE[1]} {HSIZE[2]} ]] + create_debug_port u_ila_0 probe set_property port_width 2 [get_debug_ports u_ila_0/probe31] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31] @@ -178,22 +192,27 @@ create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe37] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37] connect_debug_port u_ila_0/probe37 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/EcallFaultM ]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe38] +set_property port_width 3 [get_debug_ports u_ila_0/probe38] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38] -connect_debug_port u_ila_0/probe38 [get_nets [list wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_sd_dat_fsm/i_DAT0_Q ]] +connect_debug_port u_ila_0/probe38 [get_nets [list {HBURST[0]} {HBURST[1]} {HBURST[2]} ]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe39] +set_property port_width 2 [get_debug_ports u_ila_0/probe39] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39] -connect_debug_port u_ila_0/probe39 [get_nets [list wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_sd_dat_fsm/i_DATA_CRC16_GOOD ]] +connect_debug_port u_ila_0/probe39 [get_nets [list {HTRANS[0]} {HTRANS[1]} ]] + create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe40] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40] -connect_debug_port u_ila_0/probe40 [get_nets [list wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/i_ERROR_CRC16 ]] +connect_debug_port u_ila_0/probe40 [get_nets [list {HREADY} ]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe41] +set_property port_width 4 [get_debug_ports u_ila_0/probe41] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41] -connect_debug_port u_ila_0/probe41 [get_nets [list wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/i_ERROR_DAT_TIMES_OUT ]] +connect_debug_port u_ila_0/probe41 [get_nets [list {m_axi_awid[0]} {m_axi_awid[1]} {m_axi_awid[2]} {m_axi_awid[3]} ]] + create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe42] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42] @@ -232,26 +251,33 @@ create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe50] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50] connect_debug_port u_ila_0/probe50 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/mretM ]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe51] +set_property port_width 8 [get_debug_ports u_ila_0/probe51] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51] -connect_debug_port u_ila_0/probe51 [get_nets [list wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_clk_fsm/o_G_CLK_SD_EN ]] +connect_debug_port u_ila_0/probe51 [get_nets [list {m_axi_awlen[0]} {m_axi_awlen[1]} {m_axi_awlen[2]} {m_axi_awlen[3]} {m_axi_awlen[4]} {m_axi_awlen[5]} {m_axi_awlen[6]} {m_axi_awlen[7]} ]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe52] +set_property port_width 2 [get_debug_ports u_ila_0/probe52] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52] -connect_debug_port u_ila_0/probe52 [get_nets [list wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/o_SD_CLK ]] +connect_debug_port u_ila_0/probe52 [get_nets [list {m_axi_awburst[0]} {m_axi_awburst[1]} ]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe53] +set_property port_width 4 [get_debug_ports u_ila_0/probe53] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53] -connect_debug_port u_ila_0/probe53 [get_nets [list wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/o_SD_CMD ]] +connect_debug_port u_ila_0/probe53 [get_nets [list {m_axi_awcache[0]} {m_axi_awcache[1]} {m_axi_awcache[2]} {m_axi_awcache[3]} ]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe54] +set_property port_width 32 [get_debug_ports u_ila_0/probe54] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54] -connect_debug_port u_ila_0/probe54 [get_nets [list wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/o_SD_CMD_OE ]] +connect_debug_port u_ila_0/probe54 [get_nets [list {m_axi_awaddr[0]} {m_axi_awaddr[1]} {m_axi_awaddr[2]} {m_axi_awaddr[3]} {m_axi_awaddr[4]} {m_axi_awaddr[5]} {m_axi_awaddr[6]} {m_axi_awaddr[7]} {m_axi_awaddr[8]} {m_axi_awaddr[9]} {m_axi_awaddr[10]} {m_axi_awaddr[11]} {m_axi_awaddr[12]} {m_axi_awaddr[13]} {m_axi_awaddr[14]} {m_axi_awaddr[15]} {m_axi_awaddr[16]} {m_axi_awaddr[17]} {m_axi_awaddr[18]} {m_axi_awaddr[19]} {m_axi_awaddr[20]} {m_axi_awaddr[21]} {m_axi_awaddr[22]} {m_axi_awaddr[23]} {m_axi_awaddr[24]} {m_axi_awaddr[25]} {m_axi_awaddr[26]} {m_axi_awaddr[27]} {m_axi_awaddr[28]} {m_axi_awaddr[29]} {m_axi_awaddr[30]} {m_axi_awaddr[31]} ]] + create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe55] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55] -connect_debug_port u_ila_0/probe55 [get_nets [list wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_SD_CMD_OE ]] +connect_debug_port u_ila_0/probe55 [get_nets [list {m_axi_awvalid} ]] + + create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe56] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56] @@ -260,10 +286,12 @@ create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe57] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57] connect_debug_port u_ila_0/probe57 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/OUT2b ]] + create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe58] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58] -connect_debug_port u_ila_0/probe58 [get_nets [list wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/r_DAT_ERROR_Q ]] +connect_debug_port u_ila_0/probe58 [get_nets [list {m_axi_awready} ]] + create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe59] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59] @@ -304,20 +332,21 @@ create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe68] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe68] connect_debug_port u_ila_0/probe68 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/TXRDYb ]] + create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe69] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe69] -connect_debug_port u_ila_0/probe69 [get_nets [list wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/w_IC_EN ]] +connect_debug_port u_ila_0/probe69 [get_nets [list {m_axi_awlock} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe70] +set_property port_width 64 [get_debug_ports u_ila_0/probe70] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe70] -connect_debug_port u_ila_0/probe70 [get_nets [list wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/w_IC_RST ]] +connect_debug_port u_ila_0/probe70 [get_nets [list {m_axi_wdata[0]} {m_axi_wdata[1]} {m_axi_wdata[2]} {m_axi_wdata[3]} {m_axi_wdata[4]} {m_axi_wdata[5]} {m_axi_wdata[6]} {m_axi_wdata[7]} {m_axi_wdata[8]} {m_axi_wdata[9]} {m_axi_wdata[10]} {m_axi_wdata[11]} {m_axi_wdata[12]} {m_axi_wdata[13]} {m_axi_wdata[14]} {m_axi_wdata[15]} {m_axi_wdata[16]} {m_axi_wdata[17]} {m_axi_wdata[18]} {m_axi_wdata[19]} {m_axi_wdata[20]} {m_axi_wdata[21]} {m_axi_wdata[22]} {m_axi_wdata[23]} {m_axi_wdata[24]} {m_axi_wdata[25]} {m_axi_wdata[26]} {m_axi_wdata[27]} {m_axi_wdata[28]} {m_axi_wdata[29]} {m_axi_wdata[30]} {m_axi_wdata[31]} {m_axi_wdata[32]} {m_axi_wdata[33]} {m_axi_wdata[34]} {m_axi_wdata[35]} {m_axi_wdata[36]} {m_axi_wdata[37]} {m_axi_wdata[38]} {m_axi_wdata[39]} {m_axi_wdata[40]} {m_axi_wdata[41]} {m_axi_wdata[42]} {m_axi_wdata[43]} {m_axi_wdata[44]} {m_axi_wdata[45]} {m_axi_wdata[46]} {m_axi_wdata[47]} {m_axi_wdata[48]} {m_axi_wdata[49]} {m_axi_wdata[50]} {m_axi_wdata[51]} {m_axi_wdata[52]} {m_axi_wdata[53]} {m_axi_wdata[54]} {m_axi_wdata[55]} {m_axi_wdata[56]} {m_axi_wdata[57]} {m_axi_wdata[58]} {m_axi_wdata[59]} {m_axi_wdata[60]} {m_axi_wdata[61]} {m_axi_wdata[62]} {m_axi_wdata[63]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe71] +set_property port_width 8 [get_debug_ports u_ila_0/probe71] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe71] -connect_debug_port u_ila_0/probe71 [get_nets [list wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/w_IC_UP_DOWN ]] +connect_debug_port u_ila_0/probe71 [get_nets [list {m_axi_wstrb[0]} {m_axi_wstrb[1]} {m_axi_wstrb[2]} {m_axi_wstrb[3]} {m_axi_wstrb[4]} {m_axi_wstrb[5]} {m_axi_wstrb[6]} {m_axi_wstrb[7]} ]] create_debug_port u_ila_0 probe @@ -753,37 +782,36 @@ set_property port_width 8 [get_debug_ports u_ila_0/probe155] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe155] connect_debug_port u_ila_0/probe155 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[7]} ]] - create_debug_port u_ila_0 probe -set_property port_width 12 [get_debug_ports u_ila_0/probe156] +set_property port_width 1 [get_debug_ports u_ila_0/probe156] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe156] -connect_debug_port u_ila_0/probe156 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/requests[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[2]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[3]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[4]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[5]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[6]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[7]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[8]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[9]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[10]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[11]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[12]}]] - +connect_debug_port u_ila_0/probe156 [get_nets [list {m_axi_wlast} ]] + create_debug_port u_ila_0 probe -set_property port_width 12 [get_debug_ports u_ila_0/probe157] +set_property port_width 1 [get_debug_ports u_ila_0/probe157] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe157] -connect_debug_port u_ila_0/probe157 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[2]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[3]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[4]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[5]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[6]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[7]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[8]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[9]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[10]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[11]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[12]}]] - +connect_debug_port u_ila_0/probe157 [get_nets [list {m_axi_wvalid} ]] + create_debug_port u_ila_0 probe -set_property port_width 12 [get_debug_ports u_ila_0/probe158] +set_property port_width 1 [get_debug_ports u_ila_0/probe158] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe158] -connect_debug_port u_ila_0/probe158 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[2]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[3]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[4]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[5]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[6]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[7]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[8]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[9]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[10]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[11]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[12]}]] - +connect_debug_port u_ila_0/probe158 [get_nets [list {m_axi_wready} ]] create_debug_port u_ila_0 probe -set_property port_width 70 [get_debug_ports u_ila_0/probe159] +set_property port_width 4 [get_debug_ports u_ila_0/probe159] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe159] -connect_debug_port u_ila_0/probe159 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][10]} ]] +connect_debug_port u_ila_0/probe159 [get_nets [list {m_axi_bid[0]} {m_axi_bid[1]} {m_axi_bid[2]} {m_axi_bid[3]} ]] create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe160] +set_property port_width 2 [get_debug_ports u_ila_0/probe160] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe160] -connect_debug_port u_ila_0/probe160 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intPriority[10][0]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPriority[10][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPriority[10][2]} ]] - +connect_debug_port u_ila_0/probe160 [get_nets [list {m_axi_bresp[0]} {m_axi_bresp[1]} ]] + create_debug_port u_ila_0 probe -set_property port_width 10 [get_debug_ports u_ila_0/probe161] +set_property port_width 1 [get_debug_ports u_ila_0/probe161] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe161] -connect_debug_port u_ila_0/probe161 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[2]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[3]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[4]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[5]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[6]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[7]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[8]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[9]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[10]} ]] +connect_debug_port u_ila_0/probe161 [get_nets [list {m_axi_bvalid} ]] + create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe162] @@ -826,3 +854,78 @@ set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe169] connect_debug_port u_ila_0/probe169 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[0]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[1]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[2]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[3]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[4]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[5]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[6]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[7]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[8]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[9]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[10]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[11]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[12]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[13]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[14]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[15]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[16]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[17]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[18]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[19]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[20]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[21]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[22]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[23]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[24]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[25]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[26]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[27]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[28]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[29]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[30]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[31]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[32]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[33]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[34]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[35]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[36]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[37]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[38]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[39]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[40]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[41]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[42]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[43]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[44]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[45]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[46]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[47]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[48]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[49]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[50]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[51]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[52]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[53]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[54]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[55]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[56]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[57]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[58]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[59]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[60]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[61]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[62]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[63]}]] +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe170] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe170] +connect_debug_port u_ila_0/probe170 [get_nets [list {m_axi_bready} ]] + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe171] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe171] +connect_debug_port u_ila_0/probe171 [get_nets [list {m_axi_arid[0]} {m_axi_arid[1]} {m_axi_arid[2]} {m_axi_arid[3]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 8 [get_debug_ports u_ila_0/probe172] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe172] +connect_debug_port u_ila_0/probe172 [get_nets [list {m_axi_arlen[0]} {m_axi_arlen[1]} {m_axi_arlen[2]} {m_axi_arlen[3]} {m_axi_arlen[4]} {m_axi_arlen[5]} {m_axi_arlen[6]} {m_axi_arlen[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 3 [get_debug_ports u_ila_0/probe173] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe173] +connect_debug_port u_ila_0/probe173 [get_nets [list {m_axi_arsize[0]} {m_axi_arsize[1]} {m_axi_arsize[2]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe174] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe174] +connect_debug_port u_ila_0/probe174 [get_nets [list {m_axi_arburst[0]} {m_axi_arburst[1]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe175] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe175] +connect_debug_port u_ila_0/probe175 [get_nets [list {m_axi_arcache[0]} {m_axi_arcache[1]} {m_axi_arcache[2]} {m_axi_arcache[3]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe176] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe176] +connect_debug_port u_ila_0/probe176 [get_nets [list {m_axi_arvalid} ]] + +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe177] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe177] +connect_debug_port u_ila_0/probe177 [get_nets [list {m_axi_araddr[0]} {m_axi_araddr[1]} {m_axi_araddr[2]} {m_axi_araddr[3]} {m_axi_araddr[4]} {m_axi_araddr[5]} {m_axi_araddr[6]} {m_axi_araddr[7]} {m_axi_araddr[8]} {m_axi_araddr[9]} {m_axi_araddr[10]} {m_axi_araddr[11]} {m_axi_araddr[12]} {m_axi_araddr[13]} {m_axi_araddr[14]} {m_axi_araddr[15]} {m_axi_araddr[16]} {m_axi_araddr[17]} {m_axi_araddr[18]} {m_axi_araddr[19]} {m_axi_araddr[20]} {m_axi_araddr[21]} {m_axi_araddr[22]} {m_axi_araddr[23]} {m_axi_araddr[24]} {m_axi_araddr[25]} {m_axi_araddr[26]} {m_axi_araddr[27]} {m_axi_araddr[28]} {m_axi_araddr[29]} {m_axi_araddr[30]} {m_axi_araddr[31]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe178] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe178] +connect_debug_port u_ila_0/probe178 [get_nets [list {m_axi_arready} ]] + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe179] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe179] +connect_debug_port u_ila_0/probe179 [get_nets [list {m_axi_rid[0]} {m_axi_rid[1]} {m_axi_rid[2]} {m_axi_rid[3]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe180] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe180] +connect_debug_port u_ila_0/probe180 [get_nets [list {m_axi_rdata[0]} {m_axi_rdata[1]} {m_axi_rdata[2]} {m_axi_rdata[3]} {m_axi_rdata[4]} {m_axi_rdata[5]} {m_axi_rdata[6]} {m_axi_rdata[7]} {m_axi_rdata[8]} {m_axi_rdata[9]} {m_axi_rdata[10]} {m_axi_rdata[11]} {m_axi_rdata[12]} {m_axi_rdata[13]} {m_axi_rdata[14]} {m_axi_rdata[15]} {m_axi_rdata[16]} {m_axi_rdata[17]} {m_axi_rdata[18]} {m_axi_rdata[19]} {m_axi_rdata[20]} {m_axi_rdata[21]} {m_axi_rdata[22]} {m_axi_rdata[23]} {m_axi_rdata[24]} {m_axi_rdata[25]} {m_axi_rdata[26]} {m_axi_rdata[27]} {m_axi_rdata[28]} {m_axi_rdata[29]} {m_axi_rdata[30]} {m_axi_rdata[31]} {m_axi_rdata[32]} {m_axi_rdata[33]} {m_axi_rdata[34]} {m_axi_rdata[35]} {m_axi_rdata[36]} {m_axi_rdata[37]} {m_axi_rdata[38]} {m_axi_rdata[39]} {m_axi_rdata[40]} {m_axi_rdata[41]} {m_axi_rdata[42]} {m_axi_rdata[43]} {m_axi_rdata[44]} {m_axi_rdata[45]} {m_axi_rdata[46]} {m_axi_rdata[47]} {m_axi_rdata[48]} {m_axi_rdata[49]} {m_axi_rdata[50]} {m_axi_rdata[51]} {m_axi_rdata[52]} {m_axi_rdata[53]} {m_axi_rdata[54]} {m_axi_rdata[55]} {m_axi_rdata[56]} {m_axi_rdata[57]} {m_axi_rdata[58]} {m_axi_rdata[59]} {m_axi_rdata[60]} {m_axi_rdata[61]} {m_axi_rdata[62]} {m_axi_rdata[63]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe181] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe181] +connect_debug_port u_ila_0/probe181 [get_nets [list {m_axi_rresp[0]} {m_axi_rresp[1]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe182] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe182] +connect_debug_port u_ila_0/probe182 [get_nets [list {m_axi_rvalid} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe183] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe183] +connect_debug_port u_ila_0/probe183 [get_nets [list {m_axi_rlast} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe184] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe184] +connect_debug_port u_ila_0/probe184 [get_nets [list {m_axi_rready} ]] + diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index d299e551..c0445b20 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -70,21 +70,21 @@ module fpgaTop wire peripheral_aresetn; wire mb_reset; - wire [`AHBW-1:0] HRDATAEXT; - wire HREADYEXT; - wire HRESPEXT; - wire HSELEXT; wire HCLKOpen; wire HRESETnOpen; - wire [31:0] HADDR; - wire [`AHBW-1:0] HWDATA; - wire HWRITE; - wire [2:0] HSIZE; - wire [2:0] HBURST; +(* mark_debug = "true" *) wire [`AHBW-1:0] HRDATAEXT; +(* mark_debug = "true" *) wire HREADYEXT; +(* mark_debug = "true" *) wire HRESPEXT; +(* mark_debug = "true" *) wire HSELEXT; +(* mark_debug = "true" *) wire [31:0] HADDR; +(* mark_debug = "true" *) wire [`AHBW-1:0] HWDATA; +(* mark_debug = "true" *) wire HWRITE; +(* mark_debug = "true" *) wire [2:0] HSIZE; +(* mark_debug = "true" *) wire [2:0] HBURST; +(* mark_debug = "true" *) wire [1:0] HTRANS; +(* mark_debug = "true" *) wire HREADY; wire [3:0] HPROT; - wire [1:0] HTRANS; wire HMASTLOCK; - wire HREADY; @@ -94,41 +94,41 @@ module fpgaTop wire SDCCmdOE; wire SDCCmdOut; - wire [3:0] m_axi_awid; - wire [7:0] m_axi_awlen; - wire [2:0] m_axi_awsize; - wire [1:0] m_axi_awburst; - wire [3:0] m_axi_awcache; - wire [31:0] m_axi_awaddr; +(* mark_debug = "true" *) wire [3:0] m_axi_awid; +(* mark_debug = "true" *) wire [7:0] m_axi_awlen; +(* mark_debug = "true" *) wire [2:0] m_axi_awsize; +(* mark_debug = "true" *) wire [1:0] m_axi_awburst; +(* mark_debug = "true" *) wire [3:0] m_axi_awcache; +(* mark_debug = "true" *) wire [31:0] m_axi_awaddr; wire [2:0] m_axi_awprot; - wire m_axi_awvalid; - wire m_axi_awready; - wire m_axi_awlock; - wire [63:0] m_axi_wdata; - wire [7:0] m_axi_wstrb; - wire m_axi_wlast; - wire m_axi_wvalid; - wire m_axi_wready; - wire [3:0] m_axi_bid; - wire [1:0] m_axi_bresp; - wire m_axi_bvalid; - wire m_axi_bready; - wire [3:0] m_axi_arid; - wire [7:0] m_axi_arlen; - wire [2:0] m_axi_arsize; - wire [1:0] m_axi_arburst; +(* mark_debug = "true" *) wire m_axi_awvalid; +(* mark_debug = "true" *) wire m_axi_awready; +(* mark_debug = "true" *) wire m_axi_awlock; +(* mark_debug = "true" *) wire [63:0] m_axi_wdata; +(* mark_debug = "true" *) wire [7:0] m_axi_wstrb; +(* mark_debug = "true" *) wire m_axi_wlast; +(* mark_debug = "true" *) wire m_axi_wvalid; +(* mark_debug = "true" *) wire m_axi_wready; +(* mark_debug = "true" *) wire [3:0] m_axi_bid; +(* mark_debug = "true" *) wire [1:0] m_axi_bresp; +(* mark_debug = "true" *) wire m_axi_bvalid; +(* mark_debug = "true" *) wire m_axi_bready; +(* mark_debug = "true" *) wire [3:0] m_axi_arid; +(* mark_debug = "true" *) wire [7:0] m_axi_arlen; +(* mark_debug = "true" *) wire [2:0] m_axi_arsize; +(* mark_debug = "true" *) wire [1:0] m_axi_arburst; wire [2:0] m_axi_arprot; - wire [3:0] m_axi_arcache; - wire m_axi_arvalid; - wire [31:0] m_axi_araddr; +(* mark_debug = "true" *) wire [3:0] m_axi_arcache; +(* mark_debug = "true" *) wire m_axi_arvalid; +(* mark_debug = "true" *) wire [31:0] m_axi_araddr; wire m_axi_arlock; - wire m_axi_arready; - wire [3:0] m_axi_rid; - wire [63:0] m_axi_rdata; - wire [1:0] m_axi_rresp; - wire m_axi_rvalid; - wire m_axi_rlast; - wire m_axi_rready; +(* mark_debug = "true" *) wire m_axi_arready; +(* mark_debug = "true" *) wire [3:0] m_axi_rid; +(* mark_debug = "true" *) wire [63:0] m_axi_rdata; +(* mark_debug = "true" *) wire [1:0] m_axi_rresp; +(* mark_debug = "true" *) wire m_axi_rvalid; +(* mark_debug = "true" *) wire m_axi_rlast; +(* mark_debug = "true" *) wire m_axi_rready; wire [3:0] BUS_axi_arregion; wire [3:0] BUS_axi_arqos; diff --git a/pipelined/config/shared/wally-shared.vh b/pipelined/config/shared/wally-shared.vh index 87d67103..214c747d 100644 --- a/pipelined/config/shared/wally-shared.vh +++ b/pipelined/config/shared/wally-shared.vh @@ -102,7 +102,7 @@ // division constants `define RADIX 32'h2 -`define DIVCOPIES 32'h4 +`define DIVCOPIES 32'h5 `define DIVLEN ((`NF < `XLEN) ? (`XLEN) : (`NF + 3)) // `define DIVN (`NF < `XLEN ? `XLEN : `NF+1) // length of input `define DIVN (`NF < `XLEN ? `XLEN : `NF+3) // length of input diff --git a/pipelined/regression/testfloat.do b/pipelined/regression/testfloat.do index 00020f77..9b2c2b16 100644 --- a/pipelined/regression/testfloat.do +++ b/pipelined/regression/testfloat.do @@ -32,7 +32,7 @@ vlib work # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals # $num = the added words after the call -vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697 +vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697 vsim -voptargs=+acc work.testbenchfp -G TEST=$2 diff --git a/pipelined/regression/wave-fpu.do b/pipelined/regression/wave-fpu.do index fc8f7a35..990173c9 100644 --- a/pipelined/regression/wave-fpu.do +++ b/pipelined/regression/wave-fpu.do @@ -24,10 +24,10 @@ add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/W add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/WS add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/WCA add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/WSA -add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/Q -add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/QM -add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/QNext -add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/QMNext +add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/U +add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/UM +add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/UNext +add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/UMNext add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/* # add wave -group {Divide} -group inter0 -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/interations[0]/stage/fdivsqrtstage/* # add wave -group {Divide} -group inter0 -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/interations[0]/stage/fdivsqrtstage/otfc/otfc2/* diff --git a/pipelined/src/fpu/divshiftcalc.sv b/pipelined/src/fpu/divshiftcalc.sv deleted file mode 100644 index 8095b517..00000000 --- a/pipelined/src/fpu/divshiftcalc.sv +++ /dev/null @@ -1,42 +0,0 @@ -`include "wally-config.vh" - -module divshiftcalc( - input logic [`DIVb-(`RADIX/4):0] DivQm, - input logic [`FMTBITS-1:0] Fmt, - input logic Sqrt, - input logic [`DURLEN-1:0] DivEarlyTermShift, - input logic [`NE+1:0] DivQe, - output logic [$clog2(`NORMSHIFTSZ)-1:0] DivShiftAmt, - output logic [`NORMSHIFTSZ-1:0] DivShiftIn, - output logic DivResDenorm, - output logic [`NE+1:0] DivDenormShift -); - logic [`NE+1:0] NormShift; - - // is the result denromalized - // if the exponent is 1 then the result needs to be normalized then the result is denormalizes - assign DivResDenorm = DivQe[`NE+1]|(~|DivQe[`NE+1:0]); - - // if the result is denormalized - // 00000000x.xxxxxx... Exp = DivQe - // .00000000xxxxxxx... >> NF+1 Exp = DivQe+NF+1 - // .00xxxxxxxxxxxxx... << DivQe+NF+1 Exp = +1 - // .0000xxxxxxxxxxx... >> 1 Exp = 1 - // Left shift amount = DivQe+NF+1-1 - assign DivDenormShift = (`NE+2)'(`NF)+DivQe; - // if the result is normalized - // 00000000x.xxxxxx... Exp = DivQe - // .00000000xxxxxxx... >> NF+1 Exp = DivQe+NF+1 - // 00000000.xxxxxxx... << NF Exp = DivQe+1 - // 00000000x.xxxxxx... << NF Exp = DivQe (extra shift done afterwards) - // 00000000xx.xxxxx... << 1? Exp = DivQe-1 (determined after) - // inital Left shift amount = NF - // shift one more if the it's a minimally redundent radix 4 - one entire cycle needed for integer bit - assign NormShift = (`NE+2)'(`NF); - // if the shift amount is negitive then dont shift (keep sticky bit) - // need to multiply the early termination shift by LOGR*DIVCOPIES = left shift of log2(LOGR*DIVCOPIES) - assign DivShiftAmt = (DivResDenorm ? DivDenormShift[$clog2(`NORMSHIFTSZ)-1:0]&{$clog2(`NORMSHIFTSZ){~DivDenormShift[`NE+1]}} : NormShift[$clog2(`NORMSHIFTSZ)-1:0])+{{$clog2(`NORMSHIFTSZ)-`DURLEN-$clog2(`LOGR*`DIVCOPIES){1'b0}}, DivEarlyTermShift&{`DURLEN{~(DivDenormShift[`NE+1]|Sqrt)}}, {$clog2(`LOGR*`DIVCOPIES){1'b0}}}; - - assign DivShiftIn = {{`NF{1'b0}}, DivQm, {`NORMSHIFTSZ-`DIVb+1+(`RADIX/4)-`NF{1'b0}}}; - -endmodule diff --git a/pipelined/src/fpu/fclassify.sv b/pipelined/src/fpu/fclassify.sv index 6aaec00a..70049fcf 100644 --- a/pipelined/src/fpu/fclassify.sv +++ b/pipelined/src/fpu/fclassify.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// fclassivy.sv // // Written: me@KatherineParry.com // Modified: 7/5/2022 diff --git a/pipelined/src/fpu/fcmp.sv b/pipelined/src/fpu/fcmp.sv index 48ff536f..923a1891 100755 --- a/pipelined/src/fpu/fcmp.sv +++ b/pipelined/src/fpu/fcmp.sv @@ -1,5 +1,6 @@ /////////////////////////////////////////// +// fcmp.sv // // Written: me@KatherineParry.com // Modified: 7/5/2022 diff --git a/pipelined/src/fpu/fctrl.sv b/pipelined/src/fpu/fctrl.sv index 50961f27..8f10611a 100755 --- a/pipelined/src/fpu/fctrl.sv +++ b/pipelined/src/fpu/fctrl.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// fctrl.sv // // Written: me@KatherineParry.com // Modified: 7/5/2022 diff --git a/pipelined/src/fpu/fcvt.sv b/pipelined/src/fpu/fcvt.sv index d2967887..b7f2f672 100644 --- a/pipelined/src/fpu/fcvt.sv +++ b/pipelined/src/fpu/fcvt.sv @@ -1,5 +1,6 @@ /////////////////////////////////////////// +// fcvt.sv // // Written: me@KatherineParry.com // Modified: 7/5/2022 diff --git a/pipelined/src/fpu/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv similarity index 83% rename from pipelined/src/fpu/fdivsqrt.sv rename to pipelined/src/fpu/fdivsqrt/fdivsqrt.sv index fdd30657..5b740f5a 100644 --- a/pipelined/src/fpu/fdivsqrt.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // fdivsqrt.sv // -// Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek +// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu // Modified:13 January 2022 // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit @@ -48,8 +48,7 @@ module fdivsqrt( output logic DivBusy, output logic DivDone, output logic [`NE+1:0] QeM, - output logic [`DURLEN-1:0] EarlyTermShiftM, - output logic [`DIVb-(`RADIX/4):0] QmM + output logic [`DIVb:0] QmM // output logic [`XLEN-1:0] RemM, ); @@ -58,9 +57,9 @@ module fdivsqrt( logic [`DIVb+3:0] X; logic [`DIVN-2:0] D; // U0.N-1 logic [`DIVN-2:0] Dpreproc; - logic [`DIVb:0] FirstS, FirstSM, FirstQ, FirstQM; - logic [`DIVb-1:0] FirstC; - logic Firstqn; + logic [`DIVb:0] FirstU, FirstUM; + logic [`DIVb+1:0] FirstC; + logic Firstun; logic WZero; fdivsqrtpreproc fdivsqrtpreproc( @@ -70,11 +69,11 @@ module fdivsqrt( .clk, .reset, .FmtE, .XsE, .SqrtE, .DivBusy, .DivStart(DivStartE),.StallE, .StallM, .DivDone, .XZeroE, .YZeroE, .XNaNE, .YNaNE, - .XInfE, .YInfE, .EarlyTermShiftE(EarlyTermShiftM), .WZero); + .XInfE, .YInfE, .WZero); fdivsqrtiter fdivsqrtiter( - .clk, .Firstqn, .D, .FirstS, .FirstSM, .FirstQ, .FirstQM, .FirstC, .SqrtE, .SqrtM, + .clk, .Firstun, .D, .FirstU, .FirstUM, .FirstC, .SqrtE, .SqrtM, .X,.Dpreproc, .FirstWS(WS), .FirstWC(WC), .NextWSN, .NextWCN, .DivStart(DivStartE), .Xe(XeE), .Ye(YeE), .XZeroE, .YZeroE, .DivBusy); - fdivsqrtpostproc fdivsqrtpostproc(.WS, .WC, .D, .FirstS, .FirstSM, .FirstQ, .FirstQM, .FirstC, .Firstqn, .SqrtM, .QmM, .WZero, .DivSM); + fdivsqrtpostproc fdivsqrtpostproc(.WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, .SqrtM, .QmM, .WZero, .DivSM); endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv new file mode 100644 index 00000000..07d59be5 --- /dev/null +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv @@ -0,0 +1,58 @@ +/////////////////////////////////////////// +// fdivsqrtfgen2.sv +// +// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu +// Modified:13 January 2022 +// +// Purpose: Radix 2 F Addend Generator +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module fdivsqrtfgen2 ( + input logic up, uz, + input logic [`DIVb+1:0] C, + input logic [`DIVb:0] U, UM, + output logic [`DIVb+3:0] F +); + logic [`DIVb+3:0] FP, FN, FZ; + logic [`DIVb+3:0] SExt, SMExt, CExt; + + assign SExt = {3'b0, U}; + assign SMExt = {3'b0, UM}; + assign CExt = {2'b11, C}; // extend C from Q2.k to Q4.k + + // Generate for both positive and negative bits + assign FP = ~(SExt << 1) & CExt; + assign FN = (SMExt << 1) | (CExt & ~(CExt << 2)); + assign FZ = '0; + + // Choose which adder input will be used + + always_comb + if (up) F = FP; + else if (uz) F = FZ; + else F = FN; + +endmodule diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv new file mode 100644 index 00000000..08b2dfab --- /dev/null +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv @@ -0,0 +1,55 @@ +/////////////////////////////////////////// +// fdivsqrtfgen4.sv +// +// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu +// Modified:13 January 2022 +// +// Purpose: Radix 4 F Addend Generator +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module fdivsqrtfgen4 ( + input logic [3:0] u, + input logic [`DIVb+3:0] C, U, UM, + output logic [`DIVb+3:0] F +); + logic [`DIVb+3:0] F2, F1, F0, FN1, FN2; + + // Generate for both positive and negative bits + assign F2 = (~U << 2) & (C << 2); + assign F1 = ~(U << 1) & C; + assign F0 = '0; + assign FN1 = (UM << 1) | (C & ~(C << 3)); + assign FN2 = (UM << 2) | ((C << 2)&~(C << 4)); + + // Choose which adder input will be used + + always_comb + if (u[3]) F = F2; + else if (u[2]) F = F1; + else if (U[1]) F = FN1; + else if (u[0]) F = FN2; + else F = F0; +endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/fdivsqrtfsm.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv similarity index 91% rename from pipelined/src/fpu/fdivsqrtfsm.sv rename to pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv index 29666b9f..cc1294f2 100644 --- a/pipelined/src/fpu/fdivsqrtfsm.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // fdivsqrtfsm.sv // -// Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek +// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu // Modified:13 January 2022 // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit @@ -43,7 +43,6 @@ module fdivsqrtfsm( input logic StallE, input logic StallM, input logic WZero, - output logic [`DURLEN-1:0] EarlyTermShiftE, output logic DivDone, output logic DivBusy ); @@ -55,8 +54,6 @@ module fdivsqrtfsm( logic SpecialCase; logic [`DURLEN-1:0] cycles; - assign EarlyTermShiftE = step; - // terminate immediately on special cases assign SpecialCase = XZeroE | (YZeroE&~SqrtE) | XInfE | YInfE | XNaNE | YNaNE | (XsE&SqrtE); @@ -94,8 +91,7 @@ module fdivsqrtfsm( always_comb begin if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2 else fbits = Nf + 2 + `LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs - if (SqrtE) cycles = (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES); // ceiling(fbits / r*k) - else cycles = `FPDUR; // *** line above should work once otfc is used to put results in upper bits + cycles = (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES); end /* verilator lint_on WIDTH */ diff --git a/pipelined/src/fpu/fdivsqrtiter.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv similarity index 59% rename from pipelined/src/fpu/fdivsqrtiter.sv rename to pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv index 9c792d9d..5e1f2725 100644 --- a/pipelined/src/fpu/fdivsqrtiter.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv @@ -42,10 +42,9 @@ module fdivsqrtiter( input logic [`DIVN-2:0] Dpreproc, output logic [`DIVN-2:0] D, // U0.N-1 output logic [`DIVb+3:0] NextWSN, NextWCN, - output logic [`DIVb:0] FirstS, FirstSM, - output logic [`DIVb:0] FirstQ, FirstQM, - output logic [`DIVb-1:0] FirstC, - output logic Firstqn, + output logic [`DIVb:0] FirstU, FirstUM, + output logic [`DIVb+1:0] FirstC, + output logic Firstun, output logic [`DIVb+3:0] FirstWS, FirstWC ); @@ -54,33 +53,29 @@ module fdivsqrtiter( // WC/WS is dependent on D so 4.N-1 ie N+3 bits or N+2:0 + one more bit in fraction for possible sqrt right shift // D is 1.N-1, but the msb is always 1 so 0.N-1 or N-1 bits or N-1:0 // Dsel should match WC/WS so 4.N-1 ie N+3 bits or N+2:0 -// Q/QM/S/SM should be 1.b so b+1 bits or b:0 +// U/UM should be 1.b so b+1 bits or b:0 // C needs to be the lenght of the final fraction 0.b so b or b-1:0 /* verilator lint_off UNOPTFLAT */ logic [`DIVb+3:0] WSA[`DIVCOPIES-1:0]; // Q4.b logic [`DIVb+3:0] WCA[`DIVCOPIES-1:0]; // Q4.b logic [`DIVb+3:0] WS[`DIVCOPIES-1:0]; // Q4.b logic [`DIVb+3:0] WC[`DIVCOPIES-1:0]; // Q4.b - logic [`DIVb:0] Q[`DIVCOPIES-1:0]; // U1.b - logic [`DIVb:0] QM[`DIVCOPIES-1:0];// 1.b - logic [`DIVb:0] QNext[`DIVCOPIES-1:0];// U1.b - logic [`DIVb:0] QMNext[`DIVCOPIES-1:0];// U1.b - logic [`DIVb:0] S[`DIVCOPIES-1:0];// U1.b - logic [`DIVb:0] SM[`DIVCOPIES-1:0];// U1.b - logic [`DIVb:0] SNext[`DIVCOPIES-1:0];// U1.b - logic [`DIVb:0] SMNext[`DIVCOPIES-1:0];// U1.b - logic [`DIVb-1:0] C[`DIVCOPIES:0]; // 0.b - logic [`DIVb-1:0] initC; // 0.b - logic [`DIVCOPIES-1:0] qn; - + logic [`DIVb:0] U[`DIVCOPIES-1:0]; // U1.b + logic [`DIVb:0] UM[`DIVCOPIES-1:0];// 1.b + logic [`DIVb:0] UNext[`DIVCOPIES-1:0];// U1.b + logic [`DIVb:0] UMNext[`DIVCOPIES-1:0];// U1.b + logic [`DIVb+1:0] C[`DIVCOPIES:0]; // Q2.b + logic [`DIVb+1:0] initC; // Q2.b + logic [`DIVCOPIES-1:0] un; /* verilator lint_on UNOPTFLAT */ logic [`DIVb+3:0] WSN, WCN; // Q4.N-1 logic [`DIVb+3:0] DBar, D2, DBar2; // Q4.N-1 - logic [`DIVb:0] QMMux; - logic [`DIVb-1:0] NextC; - logic [`DIVb-1:0] CMux; - logic [`DIVb:0] SMux; + logic [`DIVb+1:0] NextC; + logic [`DIVb+1:0] CMux; + logic [`DIVb:0] UMux, UMMux; + logic [`DIVb:0] initU, initUM; + // Top Muxes and Registers // When start is asserted, the inputs are loaded into the divider. @@ -90,22 +85,24 @@ module fdivsqrtiter( // - otherwise load WSA into the flipflop // - the assumed one is added to D since it's always normalized (and X/0 is a special case handeled by result selection) // - XZeroE is used as the assumed one to avoid creating a sticky bit - all other numbers are normalized - if (`RADIX == 2) begin : nextw - assign NextWSN = {WSA[`DIVCOPIES-1][`DIVb+2:0], 1'b0}; - assign NextWCN = {WCA[`DIVCOPIES-1][`DIVb+2:0], 1'b0}; - end else begin : nextw - assign NextWSN = {WSA[`DIVCOPIES-1][`DIVb+1:0], 2'b0}; - assign NextWCN = {WCA[`DIVCOPIES-1][`DIVb+1:0], 2'b0}; - end - assign initC = 0; + assign NextWSN = WSA[`DIVCOPIES-1] << `LOGR; + assign NextWCN = WCA[`DIVCOPIES-1] << `LOGR; + + // Initialize C to -1 for sqrt and -R for division + logic [1:0] initCSqrt, initCDiv2, initCDiv4, initCUpper; + assign initCSqrt = 2'b11; + assign initCDiv2 = 2'b10; + assign initCDiv4 = 2'b10; // *** not sure why this works; seems like it should be 00 for initializing to -4 + assign initCUpper = SqrtE ? initCSqrt : (`RADIX == 4) ? initCDiv4 : initCDiv2; + assign initC = {initCUpper, {`DIVb{1'b0}}}; mux2 #(`DIVb+4) wsmux(NextWSN, X, DivStart, WSN); flopen #(`DIVb+4) wsflop(clk, DivStart|DivBusy, WSN, WS[0]); mux2 #(`DIVb+4) wcmux(NextWCN, '0, DivStart, WCN); flopen #(`DIVb+4) wcflop(clk, DivStart|DivBusy, WCN, WC[0]); flopen #(`DIVN-1) dflop(clk, DivStart, Dpreproc, D); - mux2 #(`DIVb) Cmux(C[`DIVCOPIES], initC, DivStart, CMux); - flopen #(`DIVb) cflop(clk, DivStart|DivBusy, CMux, C[0]); + mux2 #(`DIVb+2) Cmux(C[`DIVCOPIES], initC, DivStart, CMux); + flopen #(`DIVb+2) cflop(clk, DivStart|DivBusy, CMux, C[0]); // Divisor Selections // - choose the negitive version of what's being selected @@ -120,54 +117,38 @@ module fdivsqrtiter( generate for(i=0; $unsigned(i)<`DIVCOPIES; i++) begin : interations if (`RADIX == 2) begin: stage - fdivsqrtstage2 fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtM, - .WS(WS[i]), .WC(WC[i]), .WSA(WSA[i]), .WCA(WCA[i]), .Q(Q[i]), .QM(QM[i]), .QNext(QNext[i]), .QMNext(QMNext[i]), - .C(C[i]), .S(S[i]), .SM(SM[i]), .CNext(C[i+1]), .SNext(SNext[i]), .SMNext(SMNext[i]), .qn(qn[i])); + fdivsqrtstage2 fdivsqrtstage(.D, .DBar, .SqrtM, + .WS(WS[i]), .WC(WC[i]), .WSA(WSA[i]), .WCA(WCA[i]), + .C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i])); end else begin: stage logic j1; assign j1 = (i == 0 & ~C[0][`DIVb-1]); -// assign j1 = (i == 0 & C[0][`DIVb-2] & ~C[0][`DIVb-3]); fdivsqrtstage4 fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtM, .j1, - .WS(WS[i]), .WC(WC[i]), .WSA(WSA[i]), .WCA(WCA[i]), .Q(Q[i]), .QM(QM[i]), .QNext(QNext[i]), .QMNext(QMNext[i]), - .C(C[i]), .S(S[i]), .SM(SM[i]), .CNext(C[i+1]), .SNext(SNext[i]), .SMNext(SMNext[i]), .qn(qn[i])); + .WS(WS[i]), .WC(WC[i]), .WSA(WSA[i]), .WCA(WCA[i]), + .C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i])); end if(i<(`DIVCOPIES-1)) begin - if (`RADIX==2)begin - assign WS[i+1] = {WSA[i][`DIVb+2:0], 1'b0}; - assign WC[i+1] = {WCA[i][`DIVb+2:0], 1'b0}; -// assign C[i+1] = {1'b1, C[i][`DIVb-1:1]}; - end else begin - assign WS[i+1] = {WSA[i][`DIVb+1:0], 2'b0}; - assign WC[i+1] = {WCA[i][`DIVb+1:0], 2'b0}; -// assign C[i+1] = {2'b11, C[i][`DIVb-1:2]}; - end - assign Q[i+1] = QNext[i]; - assign QM[i+1] = QMNext[i]; - assign S[i+1] = SNext[i]; - assign SM[i+1] = SMNext[i]; + assign WS[i+1] = WSA[i] << `LOGR; + assign WC[i+1] = WCA[i] << `LOGR; + assign U[i+1] = UNext[i]; + assign UM[i+1] = UMNext[i]; end end endgenerate - - // if starting a new divison set Q to 0 and QM to -1 - flopenr #(`DIVb+1) Qreg(clk, DivStart, DivBusy, QNext[`DIVCOPIES-1], Q[0]); - mux2 #(`DIVb+1) QMmux(QMNext[`DIVCOPIES-1], '1, DivStart, QMMux); - flopen #(`DIVb+1) QMreg(clk, DivStart|DivBusy, QMMux, QM[0]); - - // if starting new square root, set S to 1 and SM to 0 - flopenr #(`DIVb+1) SMreg(clk, DivStart, DivBusy, SMNext[`DIVCOPIES-1], SM[0]); - mux2 #(`DIVb+1) Smux(SNext[`DIVCOPIES-1], {1'b1, {(`DIVb){1'b0}}}, DivStart, SMux); - flopen #(`DIVb+1) Sreg(clk, DivStart|DivBusy, SMux, S[0]); - + // Initialize U to 1.0 and UM to 0 for square root; U to 0 and UM to -1 for division + assign initU = SqrtE ? {1'b1, {(`DIVb){1'b0}}} : 0; + assign initUM = SqrtE ? 0 : {1'b1, {(`DIVb){1'b0}}}; + mux2 #(`DIVb+1) Umux(UNext[`DIVCOPIES-1], initU, DivStart, UMux); + mux2 #(`DIVb+1) UMmux(UMNext[`DIVCOPIES-1], initUM, DivStart, UMMux); + flopen #(`DIVb+1) UReg(clk, DivStart|DivBusy, UMux, U[0]); + flopen #(`DIVb+1) UMReg(clk, DivStart|DivBusy, UMMux, UM[0]); + assign FirstWS = WS[0]; assign FirstWC = WC[0]; - - assign FirstS = S[0]; - assign FirstSM = SM[0]; - assign FirstQ = Q[0]; - assign FirstQM = QM[0]; + assign FirstU = U[0]; + assign FirstUM = UM[0]; assign FirstC = C[0]; - assign Firstqn = qn[0]; + assign Firstun = un[0]; endmodule diff --git a/pipelined/src/fpu/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv similarity index 78% rename from pipelined/src/fpu/fdivsqrtpostproc.sv rename to pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index c4ded523..795879cb 100644 --- a/pipelined/src/fpu/fdivsqrtpostproc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // fdivsqrtpostproc.sv // -// Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek +// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu // Modified:13 January 2022 // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit @@ -33,20 +33,21 @@ module fdivsqrtpostproc( input logic [`DIVb+3:0] WS, WC, input logic [`DIVN-2:0] D, // U0.N-1 - input logic [`DIVb:0] FirstS, FirstSM, FirstQ, FirstQM, - input logic [`DIVb-1:0] FirstC, - input logic Firstqn, + input logic [`DIVb:0] FirstU, FirstUM, + input logic [`DIVb+1:0] FirstC, + input logic Firstun, input logic SqrtM, - output logic [`DIVb-(`RADIX/4):0] QmM, + output logic [`DIVb:0] QmM, output logic WZero, output logic DivSM ); logic [`DIVb+3:0] W; + logic [`DIVb:0] PreQmM; logic NegSticky; + logic weq0; // check for early termination on an exact result. If the result is not exact, the sticky should be set - logic weq0; aplusbeq0 #(`DIVb+4) wspluswceq0(WS, WC, weq0); if (`RADIX == 2) begin @@ -55,11 +56,11 @@ module fdivsqrtpostproc( logic wfeq0; logic [`DIVb+3:0] WCF, WSF; - assign FirstK = ({3'b111, FirstC} & ~({3'b111, FirstC} << 1)); - assign FZero = SqrtM ? {FirstSM[`DIVb], FirstSM, 2'b0} | {FirstK,1'b0} : {3'b1,D,{`DIVb-`DIVN+2{1'b0}}}; + assign FirstK = ({1'b1, FirstC} & ~({1'b1, FirstC} << 1)); + assign FZero = SqrtM ? {FirstUM[`DIVb], FirstUM, 2'b0} | {FirstK,1'b0} : {3'b1,D,{`DIVb-`DIVN+2{1'b0}}}; csa #(`DIVb+4) fadd(WS, WC, FZero, 1'b0, WSF, WCF); // compute {WCF, WSF} = {WS + WC + FZero}; aplusbeq0 #(`DIVb+4) wcfpluswsfeq0(WCF, WSF, wfeq0); - assign WZero = weq0|(wfeq0 & Firstqn); + assign WZero = weq0|(wfeq0 & Firstun); end else begin assign WZero = weq0; end @@ -70,12 +71,7 @@ module fdivsqrtpostproc( assign NegSticky = W[`DIVb+3]; // division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted - always_comb - if(SqrtM) // sqrt ouputs in the range (1, .5] - if(NegSticky) QmM = {FirstSM[`DIVb-1-(`RADIX/4):0], 1'b0}; - else QmM = {FirstS[`DIVb-1-(`RADIX/4):0], 1'b0}; - else - if(NegSticky) QmM = FirstQM[`DIVb-(`RADIX/4):0]; - else QmM = FirstQ[`DIVb-(`RADIX/4):0]; + assign PreQmM = NegSticky ? FirstUM : FirstU; // Select U or U-1 depending on negative sticky bit + assign QmM = SqrtM ? (PreQmM << 1) : PreQmM; endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/fdivsqrtpreproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv similarity index 98% rename from pipelined/src/fpu/fdivsqrtpreproc.sv rename to pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index b3483f32..9b357862 100644 --- a/pipelined/src/fpu/fdivsqrtpreproc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // fdivsqrtpreproc.sv // -// Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek +// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu // Modified:13 January 2022 // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv new file mode 100644 index 00000000..8a3fc659 --- /dev/null +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv @@ -0,0 +1,63 @@ +/////////////////////////////////////////// +// fdivsqrtqsel2.sv +// +// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu +// Modified:13 January 2022 +// +// Purpose: Radix 2 Quotient Digit Selection +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module fdivsqrtqsel2 ( + input logic [3:0] ps, pc, + output logic up, uz, un +); + + logic [3:0] p, g; + logic magnitude, sign, cout; + + // The quotient selection logic is presented for simplicity, not + // for efficiency. You can probably optimize your logic to + // select the proper divisor with less delay. + + // Quotient equations from EE371 lecture notes 13-20 + assign p = ps ^ pc; + assign g = ps & pc; + + //assign magnitude = ~(&p[2:0]); + assign cout = g[2] | (p[2] & (g[1] | p[1] & g[0])); + //assign sign = p[3] ^ cout; + assign magnitude = ~((ps[2]^pc[2]) & (ps[1]^pc[1]) & + (ps[0]^pc[0])); + assign sign = (ps[3]^pc[3])^ + (ps[2] & pc[2] | ((ps[2]^pc[2]) & + (ps[1]&pc[1] | ((ps[1]^pc[1]) & + (ps[0]&pc[0]))))); + + // Produce digit = +1, 0, or -1 + assign up = magnitude & ~sign; + assign uz = ~magnitude; + assign un = magnitude & sign; +endmodule diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv new file mode 100644 index 00000000..f0a6cae0 --- /dev/null +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv @@ -0,0 +1,112 @@ +/////////////////////////////////////////// +// fdivsqrtqsel4.sv +// +// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu +// Modified:13 January 2022 +// +// Purpose: Radix 4 Quotient Digit Selection +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module fdivsqrtqsel4 ( + input logic [`DIVN-2:0] D, + input logic [4:0] Smsbs, + input logic [`DIVb+3:0] WS, WC, + input logic Sqrt, j1, + output logic [3:0] u +); + logic [6:0] Wmsbs; + logic [7:0] PreWmsbs; + logic [2:0] Dmsbs, A; + + assign PreWmsbs = WC[`DIVb+3:`DIVb-4] + WS[`DIVb+3:`DIVb-4]; + assign Wmsbs = PreWmsbs[7:1]; + assign Dmsbs = D[`DIVN-2:`DIVN-4];//|{3{D[`DIVN-2]&Sqrt}}; + // D = 0001.xxx... + // Dmsbs = | | + // W = xxxx.xxx... + // Wmsbs = | | + + logic [3:0] USel4[1023:0]; + + always_comb begin + integer a, w, i, w2; + for(a=0; a<8; a++) + for(w=0; w<128; w++)begin + i = a*128+w; + w2 = w-128*(w>=64); // convert to two's complement + case(a) + 0: if($signed(w2)>=$signed(12)) USel4[i] = 4'b1000; + else if(w2>=4) USel4[i] = 4'b0100; + else if(w2>=-4) USel4[i] = 4'b0000; + else if(w2>=-13) USel4[i] = 4'b0010; + else USel4[i] = 4'b0001; + 1: if(w2>=14) USel4[i] = 4'b1000; + else if(w2>=4) USel4[i] = 4'b0100; + else if(w2>=-4) USel4[i] = 4'b0000; + else if(w2>=-14) USel4[i] = 4'b0010; + else USel4[i] = 4'b0001; + 2: if(w2>=16) USel4[i] = 4'b1000; + else if(w2>=4) USel4[i] = 4'b0100; + else if(w2>=-6) USel4[i] = 4'b0000; + else if(w2>=-16) USel4[i] = 4'b0010; + else USel4[i] = 4'b0001; + 3: if(w2>=16) USel4[i] = 4'b1000; + else if(w2>=4) USel4[i] = 4'b0100; + else if(w2>=-6) USel4[i] = 4'b0000; + else if(w2>=-17) USel4[i] = 4'b0010; + else USel4[i] = 4'b0001; + 4: if(w2>=18) USel4[i] = 4'b1000; + else if(w2>=6) USel4[i] = 4'b0100; + else if(w2>=-6) USel4[i] = 4'b0000; + else if(w2>=-18) USel4[i] = 4'b0010; + else USel4[i] = 4'b0001; + 5: if(w2>=20) USel4[i] = 4'b1000; + else if(w2>=6) USel4[i] = 4'b0100; + else if(w2>=-8) USel4[i] = 4'b0000; + else if(w2>=-20) USel4[i] = 4'b0010; + else USel4[i] = 4'b0001; + 6: if(w2>=20) USel4[i] = 4'b1000; + else if(w2>=8) USel4[i] = 4'b0100; + else if(w2>=-8) USel4[i] = 4'b0000; + else if(w2>=-22) USel4[i] = 4'b0010; + else USel4[i] = 4'b0001; + 7: if(w2>=24) USel4[i] = 4'b1000; + else if(w2>=8) USel4[i] = 4'b0100; + else if(w2>=-8) USel4[i] = 4'b0000; + else if(w2>=-22) USel4[i] = 4'b0010; + else USel4[i] = 4'b0001; + endcase + end + end + always_comb + if (Sqrt) begin + if (j1) A = 3'b101; + else if (Smsbs == 5'b10000) A = 3'b111; + else A = Smsbs[2:0]; + end else A = Dmsbs; + assign u = USel4[{A,Wmsbs}]; + +endmodule diff --git a/pipelined/src/fpu/fdivsqrtstage2.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv similarity index 72% rename from pipelined/src/fpu/fdivsqrtstage2.sv rename to pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv index bdabb8ae..987f2357 100644 --- a/pipelined/src/fpu/fdivsqrtstage2.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv @@ -33,47 +33,47 @@ /* verilator lint_off UNOPTFLAT */ module fdivsqrtstage2 ( input logic [`DIVN-2:0] D, - input logic [`DIVb+3:0] DBar, D2, DBar2, - input logic [`DIVb:0] Q, QM, - input logic [`DIVb:0] S, SM, + input logic [`DIVb+3:0] DBar, + input logic [`DIVb:0] U, UM, input logic [`DIVb+3:0] WS, WC, - input logic [`DIVb-1:0] C, + input logic [`DIVb+1:0] C, input logic SqrtM, - output logic [`DIVb:0] QNext, QMNext, - output logic qn, - output logic [`DIVb-1:0] CNext, - output logic [`DIVb:0] SNext, SMNext, + output logic un, + output logic [`DIVb+1:0] CNext, + output logic [`DIVb:0] UNext, UMNext, output logic [`DIVb+3:0] WSA, WCA ); /* verilator lint_on UNOPTFLAT */ logic [`DIVb+3:0] Dsel; - logic qp, qz; + logic up, uz; logic [`DIVb+3:0] F; logic [`DIVb+3:0] AddIn; - assign CNext = {1'b1, C[`DIVb-1:1]}; + assign CNext = {1'b1, C[`DIVb+1:1]}; // Qmient Selection logic - // Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm) + // Given partial remainder, select digit of +1, 0, or -1 (up, uz, un) // q encoding: // 1000 = +2 // 0100 = +1 // 0000 = 0 // 0010 = -1 // 0001 = -2 - qsel2 qsel2(WS[`DIVb+3:`DIVb], WC[`DIVb+3:`DIVb], qp, qz, qn); - fgen2 fgen2(.sp(qp), .sz(qz), .C(CNext), .S, .SM, .F); + fdivsqrtqsel2 qsel2(WS[`DIVb+3:`DIVb], WC[`DIVb+3:`DIVb], up, uz, un); + fdivsqrtfgen2 fgen2(.up, .uz, .C(CNext), .U, .UM, .F); + + always_comb + if (up) Dsel = DBar; + else if (uz) Dsel = '0; // qz + else Dsel = {3'b0, 1'b1, D, {`DIVb-`DIVN+1{1'b0}}}; // un - assign Dsel = {`DIVb+4{~qz}}&(qp ? DBar : {3'b0, 1'b1, D, {`DIVb-`DIVN+1{1'b0}}}); // Partial Product Generation // WSA, WCA = WS + WC - qD assign AddIn = SqrtM ? F : Dsel; - csa #(`DIVb+4) csa(WS, WC, AddIn, qp&~SqrtM, WSA, WCA); + csa #(`DIVb+4) csa(WS, WC, AddIn, up&~SqrtM, WSA, WCA); - // *** dh 8/29/22: will need to trim down to just sotfc - otfc2 otfc2(.qp, .qz, .Q, .QM, .QNext, .QMNext); - sotfc2 sotfc2(.sp(qp), .sz(qz), .C(CNext), .S, .SM, .SNext, .SMNext); + fdivsqrtuotfc2 uotfc2(.up, .uz, .C(CNext), .U, .UM, .UNext, .UMNext); endmodule diff --git a/pipelined/src/fpu/fdivsqrtstage4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv similarity index 75% rename from pipelined/src/fpu/fdivsqrtstage4.sv rename to pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv index bb2f02f8..9fa655c3 100644 --- a/pipelined/src/fpu/fdivsqrtstage4.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv @@ -34,42 +34,38 @@ module fdivsqrtstage4 ( input logic [`DIVN-2:0] D, input logic [`DIVb+3:0] DBar, D2, DBar2, - input logic [`DIVb:0] Q, QM, - input logic [`DIVb:0] S, SM, + input logic [`DIVb:0] U, UM, input logic [`DIVb+3:0] WS, WC, - input logic [`DIVb-1:0] C, - output logic [`DIVb-1:0] CNext, + input logic [`DIVb+1:0] C, + output logic [`DIVb+1:0] CNext, input logic SqrtM, j1, - output logic [`DIVb:0] QNext, QMNext, - output logic qn, - output logic [`DIVb:0] SNext, SMNext, + output logic un, + output logic [`DIVb:0] UNext, UMNext, output logic [`DIVb+3:0] WSA, WCA ); /* verilator lint_on UNOPTFLAT */ logic [`DIVb+3:0] Dsel; - logic [3:0] q; + logic [3:0] u; logic [`DIVb+3:0] F; logic [`DIVb+3:0] AddIn; logic [4:0] Smsbs; logic CarryIn; + assign CNext = {2'b11, C[`DIVb+1:2]}; - assign CNext = {2'b11, C[`DIVb-1:2]}; - - // Qmient Selection logic - // Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm) - // q encoding: + // Digit Selection logic + // u encoding: // 1000 = +2 // 0100 = +1 // 0000 = 0 // 0010 = -1 // 0001 = -2 - assign Smsbs = S[`DIVb:`DIVb-4]; - qsel4 qsel4(.D, .Smsbs, .WS, .WC, .Sqrt(SqrtM), .j1, .q); - fgen4 fgen4(.s(q), .C({4'b1111, CNext}), .S({3'b000, S}), .SM({3'b000, SM}), .F); + assign Smsbs = U[`DIVb:`DIVb-4]; + fdivsqrtqsel4 qsel4(.D, .Smsbs, .WS, .WC, .Sqrt(SqrtM), .j1, .u); + fdivsqrtfgen4 fgen4(.u, .C({2'b11, CNext}), .U({3'b000, U}), .UM({3'b000, UM}), .F); always_comb - case (q) + case (u) 4'b1000: Dsel = DBar2; 4'b0100: Dsel = DBar; 4'b0000: Dsel = '0; @@ -81,11 +77,12 @@ module fdivsqrtstage4 ( // Partial Product Generation // WSA, WCA = WS + WC - qD assign AddIn = SqrtM ? F : Dsel; - assign CarryIn = ~SqrtM & (q[3] | q[2]); // +1 for 2's complement of -D and -2D + assign CarryIn = ~SqrtM & (u[3] | u[2]); // +1 for 2's complement of -D and -2D csa #(`DIVb+4) csa(WS, WC, AddIn, CarryIn, WSA, WCA); - otfc4 otfc4(.q, .Q, .QM, .QNext, .QMNext); - sotfc4 sotfc4(.s(q), .Sqrt(SqrtM), .C({1'b1, CNext}), .S, .SM, .SNext, .SMNext); + fdivsqrtuotfc4 fdivsqrtuotfc4(.u, .Sqrt(SqrtM), .C(CNext[`DIVb:0]), .U, .UM, .UNext, .UMNext); + + assign un = 0; // unused for radix 4 endmodule diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv new file mode 100644 index 00000000..8a7a4922 --- /dev/null +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv @@ -0,0 +1,61 @@ +/////////////////////////////////////////// +// fdivsqrtuotfc2.sv +// +// Written: me@KatherineParry.com, cturek@hmc.edu +// Modified:7/14/2022 +// +// Purpose: Radix 2 unified on-the-fly converter +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +/////////////////////////////// +// Unified OTFC, Radix 2 // +/////////////////////////////// +module fdivsqrtuotfc2( + input logic up, uz, + input logic [`DIVb+1:0] C, + input logic [`DIVb:0] U, UM, + output logic [`DIVb:0] UNext, UMNext +); + // The on-the-fly converter transfers the divsqrt + // bits to the quotient as they come. + logic [`DIVb:0] K; + + assign K = (C[`DIVb:0] & ~(C[`DIVb:0] << 1)); + + always_comb begin + if (up) begin + UNext = U | K; + UMNext = U; + end else if (uz) begin + UNext = U; + UMNext = UM | K; + end else begin // If up and uz are not true, then un is + UNext = UM | K; + UMNext = UM; + end + end + +endmodule diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv new file mode 100644 index 00000000..c3c64bbb --- /dev/null +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv @@ -0,0 +1,68 @@ +/////////////////////////////////////////// +// fdivsqrtuotfc4.sv +// +// Written: me@KatherineParry.com, cturek@hmc.edu +// Modified:7/14/2022 +// +// Purpose: Radix 4 unified on-the-fly converter +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module fdivsqrtuotfc4( + input logic [3:0] u, + input logic Sqrt, + input logic [`DIVb:0] U, UM, + input logic [`DIVb:0] C, + output logic [`DIVb:0] UNext, UMNext +); + // The on-the-fly converter transfers the square root + // bits to the quotient as they come. + // Use this otfc for division and square root. + + logic [`DIVb:0] K1, K2, K3; + assign K1 = (C&~(C << 1)); // K + assign K2 = ((C << 1)&~(C << 2)); // 2K + assign K3 = (C & ~(C << 2)); // 3K + + always_comb begin + if (u[3]) begin + UNext = U | K2; + UMNext = U | K1; + end else if (u[2]) begin + UNext = U | K1; + UMNext = U; + end else if (u[1]) begin + UNext = UM | K3; + UMNext = UM | K2; + end else if (u[0]) begin + UNext = UM | K2; + UMNext = UM | K1; + end else begin // digit = 0 + UNext = U; + UMNext = UM | K3; + end + end + +endmodule diff --git a/pipelined/src/fpu/fhazard.sv b/pipelined/src/fpu/fhazard.sv index 690e04eb..4b61f2bf 100644 --- a/pipelined/src/fpu/fhazard.sv +++ b/pipelined/src/fpu/fhazard.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// fpuhazard.sv +// fhazard.sv // // Written: me@KatherineParry.com 19 May 2021 // Modified: diff --git a/pipelined/src/fpu/flags.sv b/pipelined/src/fpu/flags.sv index 73cc3ae3..952e0c02 100644 --- a/pipelined/src/fpu/flags.sv +++ b/pipelined/src/fpu/flags.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// flags.sv // // Written: me@KatherineParry.com // Modified: 7/5/2022 diff --git a/pipelined/src/fpu/fma.sv b/pipelined/src/fpu/fma/fma.sv similarity index 99% rename from pipelined/src/fpu/fma.sv rename to pipelined/src/fpu/fma/fma.sv index d12f497e..fa71d905 100644 --- a/pipelined/src/fpu/fma.sv +++ b/pipelined/src/fpu/fma/fma.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// fma.sv // // Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu // Modified: diff --git a/pipelined/src/fpu/fmaadd.sv b/pipelined/src/fpu/fma/fmaadd.sv similarity index 99% rename from pipelined/src/fpu/fmaadd.sv rename to pipelined/src/fpu/fma/fmaadd.sv index af7b15bf..2b5d2c4a 100644 --- a/pipelined/src/fpu/fmaadd.sv +++ b/pipelined/src/fpu/fma/fmaadd.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// fmaadd.sv // // Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu // Modified: diff --git a/pipelined/src/fpu/fmaalign.sv b/pipelined/src/fpu/fma/fmaalign.sv similarity index 99% rename from pipelined/src/fpu/fmaalign.sv rename to pipelined/src/fpu/fma/fmaalign.sv index f7c84999..6c657738 100644 --- a/pipelined/src/fpu/fmaalign.sv +++ b/pipelined/src/fpu/fma/fmaalign.sv @@ -1,5 +1,6 @@ /////////////////////////////////////////// +// fmaalign.sv // // Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu // Modified: diff --git a/pipelined/src/fpu/fmaexpadd.sv b/pipelined/src/fpu/fma/fmaexpadd.sv similarity index 99% rename from pipelined/src/fpu/fmaexpadd.sv rename to pipelined/src/fpu/fma/fmaexpadd.sv index d39dfadd..33919d7a 100644 --- a/pipelined/src/fpu/fmaexpadd.sv +++ b/pipelined/src/fpu/fma/fmaexpadd.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// fmaexpadd.sv // // Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu // Modified: diff --git a/pipelined/src/fpu/fmalza.sv b/pipelined/src/fpu/fma/fmalza.sv similarity index 99% rename from pipelined/src/fpu/fmalza.sv rename to pipelined/src/fpu/fma/fmalza.sv index 8e92a5dc..1f6677dd 100644 --- a/pipelined/src/fpu/fmalza.sv +++ b/pipelined/src/fpu/fma/fmalza.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// fmalza.sv // // Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu // Modified: diff --git a/pipelined/src/fpu/fmamult.sv b/pipelined/src/fpu/fma/fmamult.sv similarity index 99% rename from pipelined/src/fpu/fmamult.sv rename to pipelined/src/fpu/fma/fmamult.sv index 1e1b0981..071b3e6c 100644 --- a/pipelined/src/fpu/fmamult.sv +++ b/pipelined/src/fpu/fma/fmamult.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// fmamult.sv // // Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu // Modified: diff --git a/pipelined/src/fpu/fmasign.sv b/pipelined/src/fpu/fma/fmasign.sv similarity index 99% rename from pipelined/src/fpu/fmasign.sv rename to pipelined/src/fpu/fma/fmasign.sv index 936eea21..aaeeb15c 100644 --- a/pipelined/src/fpu/fmasign.sv +++ b/pipelined/src/fpu/fma/fmasign.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// fmasign.sv // // Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu // Modified: diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index bfc6af0e..b6eb25d2 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// fpu.sv // // Written: me@KatherineParry.com, James Stine, Brett Mathis // Modified: 6/23/2021 @@ -123,11 +124,10 @@ module fpu ( logic [`CVTLEN-1:0] CvtLzcInE, CvtLzcInM; // input to the Leading Zero Counter (priority encoder) //divide signals - logic [`DIVb-(`RADIX/4):0] QmM; + logic [`DIVb:0] QmM; logic [`NE+1:0] QeE, QeM; logic DivSE, DivSM; logic DivDoneM; - logic [`DURLEN-1:0] EarlyTermShiftM; // result and flag signals logic [`XLEN-1:0] ClassResE; // classify result @@ -260,7 +260,7 @@ module fpu ( fdivsqrt fdivsqrt(.clk, .reset, .FmtE, .XmE, .YmE, .XeE, .YeE, .SqrtE(OpCtrlE[0]), .SqrtM(OpCtrlM[0]), .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .DivStartE(DivStartE), .XsE, .StallE, .StallM, .DivSM, .DivBusy(FDivBusyE), .QeM, //***change divbusyE to M signal - .EarlyTermShiftM, .QmM, .DivDone(DivDoneM)); + .QmM, .DivDone(DivDoneM)); // compare // - fmin/fmax // - flt/fle/feq @@ -364,7 +364,7 @@ module fpu ( assign FpLoadStoreM = FResSelM[1]; - postprocess postprocess(.Xs(XsM), .Ys(YsM), .Ze(ZeM), .Xm(XmM), .Ym(YmM), .Zm(ZmM), .Frm(FrmM), .Fmt(FmtM), .FmaPe(PeM), .DivEarlyTermShift(EarlyTermShiftM), + postprocess postprocess(.Xs(XsM), .Ys(YsM), .Ze(ZeM), .Xm(XmM), .Ym(YmM), .Zm(ZmM), .Frm(FrmM), .Fmt(FmtM), .FmaPe(PeM), .FmaZmS(ZmStickyM), .FmaKillProd(KillProdM), .XZero(XZeroM), .YZero(YZeroM), .ZZero(ZZeroM), .XInf(XInfM), .YInf(YInfM), .DivQm(QmM), .FmaSs(SsM), .ZInf(ZInfM), .XNaN(XNaNM), .YNaN(YNaNM), .ZNaN(ZNaNM), .XSNaN(XSNaNM), .YSNaN(YSNaNM), .ZSNaN(ZSNaNM), .FmaSm(SmM), .DivQe(QeM), .DivDone(DivDoneM), .FmaNegSum(NegSumM), .FmaInvA(InvAM), .ZDenorm(ZDenormM), .FmaAs(AsM), .FmaPs(PsM), .OpCtrl(OpCtrlM), .FmaSCnt(SCntM), .FmaSe(SeM), diff --git a/pipelined/src/fpu/fregfile.sv b/pipelined/src/fpu/fregfile.sv index 00c89ff5..f738fc8a 100644 --- a/pipelined/src/fpu/fregfile.sv +++ b/pipelined/src/fpu/fregfile.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// fregfile.sv // // Written: David_Harris@hmc.edu 9 January 2021 // Modified: James Stine diff --git a/pipelined/src/fpu/fsgninj.sv b/pipelined/src/fpu/fsgninj.sv index a5b7e774..a8556998 100755 --- a/pipelined/src/fpu/fsgninj.sv +++ b/pipelined/src/fpu/fsgninj.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// fsgninj.sv // // Written: me@KatherineParry.com // Modified: 6/23/2021 diff --git a/pipelined/src/fpu/normshift.sv b/pipelined/src/fpu/normshift.sv index f382eed3..0d23d2f7 100644 --- a/pipelined/src/fpu/normshift.sv +++ b/pipelined/src/fpu/normshift.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// normshift.sv // // Written: me@KatherineParry.com // Modified: 7/5/2022 @@ -65,7 +66,7 @@ // - plus 1 to shift out the first 1 module normshift( - input logic [$clog2(`NORMSHIFTSZ)-1:0] ShiftAmt, // normalization shift count + input logic [`LOGNORMSHIFTSZ-1:0] ShiftAmt, // normalization shift count input logic [`NORMSHIFTSZ-1:0] ShiftIn, // is the sum zero output logic [`NORMSHIFTSZ-1:0] Shifted // is the sum zero ); diff --git a/pipelined/src/fpu/otfc.sv b/pipelined/src/fpu/otfc.sv deleted file mode 100644 index d006278a..00000000 --- a/pipelined/src/fpu/otfc.sv +++ /dev/null @@ -1,177 +0,0 @@ -/////////////////////////////////////////// -// otfc.sv -// -// Written: me@KatherineParry.com, cturek@hmc.edu -// Modified:7/14/2022 -// -// Purpose: On the fly conversion -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module otfc2 ( - input logic qp, qz, - input logic [`DIVb:0] Q, QM, - output logic [`DIVb:0] QNext, QMNext -); - // The on-the-fly converter transfers the quotient - // bits to the quotient as they come. - // Use this otfc for division only. - logic [`DIVb-1:0] QR, QMR; - - assign QR = Q[`DIVb-1:0]; - assign QMR = QM[`DIVb-1:0]; // Shifted Q and QM - - always_comb begin - if (qp) begin - QNext = {QR, 1'b1}; - QMNext = {QR, 1'b0}; - end else if (qz) begin - QNext = {QR, 1'b0}; - QMNext = {QMR, 1'b1}; - end else begin // If qp and qz are not true, then qn is - QNext = {QMR, 1'b1}; - QMNext = {QMR, 1'b0}; - end - end - -endmodule - -/////////////////////////////// -// Square Root OTFC, Radix 2 // -/////////////////////////////// -module sotfc2( - input logic sp, sz, - input logic [`DIVb-1:0] C, - input logic [`DIVb:0] S, SM, - output logic [`DIVb:0] SNext, SMNext -); - // The on-the-fly converter transfers the square root - // bits to the quotient as they come. - // Use this otfc for division and square root. - logic [`DIVb:0] CExt; - - assign CExt = {1'b1, C}; - - always_comb begin - if (sp) begin - SNext = S | (CExt & ~(CExt << 1)); - SMNext = S; - end else if (sz) begin - SNext = S; - SMNext = SM | (CExt & ~(CExt << 1)); - end else begin // If sp and sz are not true, then sn is - SNext = SM | (CExt & ~(CExt << 1)); - SMNext = SM; - end - end - -endmodule - -module otfc4 ( - input logic [3:0] q, - input logic [`DIVb:0] Q, QM, - output logic [`DIVb:0] QNext, QMNext -); - - // The on-the-fly converter transfers the quotient - // bits to the quotient as they come. - // - // This code follows the psuedocode presented in the - // floating point chapter of the book. Right now, - // it is written for Radix-4 division. - // - // QM is Q-1. It allows us to write negative bits - // without using a costly CPA. - - // QR and QMR are the shifted versions of Q and QM. - // They are treated as [N-1:r] size signals, and - // discard the r most significant bits of Q and QM. - logic [`DIVb-2:0] QR, QMR; - - // shift Q (quotent) and QM (quotent-1) - // if q = 2 Q = {Q, 10} QM = {Q, 01} - // else if q = 1 Q = {Q, 01} QM = {Q, 00} - // else if q = 0 Q = {Q, 00} QM = {QM, 11} - // else if q = -1 Q = {QM, 11} QM = {QM, 10} - // else if q = -2 Q = {QM, 10} QM = {QM, 01} - - assign QR = Q[`DIVb-2:0]; - assign QMR = QM[`DIVb-2:0]; // Shifted Q and QM - always_comb begin - if (q[3]) begin // +2 - QNext = {QR, 2'b10}; - QMNext = {QR, 2'b01}; - end else if (q[2]) begin // +1 - QNext = {QR, 2'b01}; - QMNext = {QR, 2'b00}; - end else if (q[1]) begin // -1 - QNext = {QMR, 2'b11}; - QMNext = {QMR, 2'b10}; - end else if (q[0]) begin // -2 - QNext = {QMR, 2'b10}; - QMNext = {QMR, 2'b01}; - end else begin // 0 - QNext = {QR, 2'b00}; - QMNext = {QMR, 2'b11}; - end - end - // Final Qmeint is in the range [.5, 2) - -endmodule - -/////////////////////////////// -// Square Root OTFC, Radix 4 // -/////////////////////////////// -module sotfc4( - input logic [3:0] s, - input logic Sqrt, - input logic [`DIVb:0] S, SM, - input logic [`DIVb:0] C, - output logic [`DIVb:0] SNext, SMNext -); - // The on-the-fly converter transfers the square root - // bits to the quotient as they come. - // Use this otfc for division and square root. - - always_comb begin - if (s[3]) begin - SNext = S | ((C << 1)&~(C << 2)); - SMNext = S | (C&~(C << 1)); - end else if (s[2]) begin - SNext = S | (C&~(C << 1)); - SMNext = S; - end else if (s[1]) begin - SNext = SM | (C&~(C << 2)); - SMNext = SM | ((C << 1)&~(C << 2)); - end else if (s[0]) begin - SNext = SM | ((C << 1)&~(C << 2)); - SMNext = SM | (C&~(C << 1)); - end else begin // If sp and sn are not true, then sz is - SNext = S; - SMNext = SM | (C & ~(C << 2)); - end - end - -endmodule diff --git a/pipelined/src/fpu/cvtshiftcalc.sv b/pipelined/src/fpu/postproc/cvtshiftcalc.sv similarity index 99% rename from pipelined/src/fpu/cvtshiftcalc.sv rename to pipelined/src/fpu/postproc/cvtshiftcalc.sv index aef894f9..88382bdc 100644 --- a/pipelined/src/fpu/cvtshiftcalc.sv +++ b/pipelined/src/fpu/postproc/cvtshiftcalc.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// cvtshiftcalc.sv // // Written: me@KatherineParry.com // Modified: 7/5/2022 diff --git a/pipelined/src/fpu/postproc/divshiftcalc.sv b/pipelined/src/fpu/postproc/divshiftcalc.sv new file mode 100644 index 00000000..2b1128ea --- /dev/null +++ b/pipelined/src/fpu/postproc/divshiftcalc.sv @@ -0,0 +1,80 @@ +/////////////////////////////////////////// +// divshiftcalc.sv +// +// Written: me@KatherineParry.com +// Modified: 7/5/2022 +// +// Purpose: Conversion shift calculation +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +////////////////////////////////////////////////////////////////////////////////////////////////`include "wally-config.vh" + +`include "wally-config.vh" + +module divshiftcalc( + input logic [`DIVb:0] DivQm, + input logic [`FMTBITS-1:0] Fmt, + input logic Sqrt, + input logic [`NE+1:0] DivQe, + output logic [`LOGNORMSHIFTSZ-1:0] DivShiftAmt, + output logic [`NORMSHIFTSZ-1:0] DivShiftIn, + output logic DivResDenorm, + output logic DivDenormShiftPos +); + logic [`LOGNORMSHIFTSZ-1:0] NormShift, DivDenormShiftAmt; + logic [`NE+1:0] DivDenormShift; + + logic [`DURLEN-1:0] DivEarlyTermShift = 0; + + // is the result denromalized + // if the exponent is 1 then the result needs to be normalized then the result is denormalizes + assign DivResDenorm = DivQe[`NE+1]|(~|DivQe[`NE+1:0]); + + // if the result is denormalized + // 00000000x.xxxxxx... Exp = DivQe + // .00000000xxxxxxx... >> NF+1 Exp = DivQe+NF+1 + // .00xxxxxxxxxxxxx... << DivQe+NF+1 Exp = +1 + // .0000xxxxxxxxxxx... >> 1 Exp = 1 + // Left shift amount = DivQe+NF+1-1 + assign DivDenormShift = (`NE+2)'(`NF)+DivQe; + assign DivDenormShiftPos = ~DivDenormShift[`NE+1]; + + // if the result is normalized + // 00000000x.xxxxxx... Exp = DivQe + // .00000000xxxxxxx... >> NF+1 Exp = DivQe+NF+1 + // 00000000.xxxxxxx... << NF Exp = DivQe+1 + // 00000000x.xxxxxx... << NF Exp = DivQe (extra shift done afterwards) + // 00000000xx.xxxxx... << 1? Exp = DivQe-1 (determined after) + // inital Left shift amount = NF + // shift one more if the it's a minimally redundent radix 4 - one entire cycle needed for integer bit + assign NormShift = (`LOGNORMSHIFTSZ)'(`NF); + + // if the shift amount is negitive then don't shift (keep sticky bit) + // need to multiply the early termination shift by LOGR*DIVCOPIES = left shift of log2(LOGR*DIVCOPIES) + assign DivDenormShiftAmt = DivDenormShiftPos ? DivDenormShift[`LOGNORMSHIFTSZ-1:0] : '0; + assign DivShiftAmt = DivResDenorm ? DivDenormShiftAmt : NormShift; + + if (`RADIX == 4) + assign DivShiftIn = {{`NF{1'b0}}, DivQm[`DIVb-1:0], {`NORMSHIFTSZ-`DIVb+2-`NF{1'b0}}}; + else + assign DivShiftIn = {{`NF{1'b0}}, DivQm, {`NORMSHIFTSZ-`DIVb+1-`NF{1'b0}}}; +endmodule diff --git a/pipelined/src/fpu/fmashiftcalc.sv b/pipelined/src/fpu/postproc/fmashiftcalc.sv similarity index 99% rename from pipelined/src/fpu/fmashiftcalc.sv rename to pipelined/src/fpu/postproc/fmashiftcalc.sv index a1c0a276..03209ca9 100644 --- a/pipelined/src/fpu/fmashiftcalc.sv +++ b/pipelined/src/fpu/postproc/fmashiftcalc.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// fmashiftcalc.sv // // Written: me@KatherineParry.com // Modified: 7/5/2022 diff --git a/pipelined/src/fpu/negateintres.sv b/pipelined/src/fpu/postproc/negateintres.sv similarity index 98% rename from pipelined/src/fpu/negateintres.sv rename to pipelined/src/fpu/postproc/negateintres.sv index 7a696b37..5e8959ff 100644 --- a/pipelined/src/fpu/negateintres.sv +++ b/pipelined/src/fpu/postproc/negateintres.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// negateintres.sv // // Written: me@KatherineParry.com // Modified: 7/5/2022 diff --git a/pipelined/src/fpu/postprocess.sv b/pipelined/src/fpu/postproc/postprocess.sv similarity index 93% rename from pipelined/src/fpu/postprocess.sv rename to pipelined/src/fpu/postproc/postprocess.sv index 8039f7c3..ee18c4bc 100644 --- a/pipelined/src/fpu/postprocess.sv +++ b/pipelined/src/fpu/postproc/postprocess.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// postprocess.sv // // Written: me@KatherineParry.com // Modified: 7/5/2022 @@ -56,11 +57,10 @@ module postprocess ( input logic FmaSs, input logic [$clog2(3*`NF+7)-1:0] FmaSCnt, // the normalization shift count //divide signals - input logic [`DURLEN-1:0] DivEarlyTermShift, input logic DivS, input logic DivDone, input logic [`NE+1:0] DivQe, - input logic [`DIVb-(`RADIX/4):0] DivQm, + input logic [`DIVb:0] DivQm, // conversion signals input logic CvtCs, // the result's sign input logic [`NE:0] CvtCe, // the calculated expoent @@ -84,7 +84,7 @@ module postprocess ( logic [`CORRSHIFTSZ-1:0] Mf; // corectly shifted fraction logic [`NE+1:0] FullRe; // Re with bits to determine sign and overflow logic UfPlus1; // do you add one (for determining underflow flag) - logic [$clog2(`NORMSHIFTSZ)-1:0] ShiftAmt; // normalization shift count + logic [`LOGNORMSHIFTSZ-1:0] ShiftAmt; // normalization shift count logic [`NORMSHIFTSZ-1:0] ShiftIn; // is the sum zero logic [`NORMSHIFTSZ-1:0] Shifted; // the shifted result logic Plus1; // add one to the final result? @@ -99,12 +99,12 @@ module postprocess ( logic FmaPreResultDenorm; // is the result denormalized - calculated before LZA corection logic [$clog2(3*`NF+7)-1:0] FmaShiftAmt; // normalization shift count // division singals - logic [$clog2(`NORMSHIFTSZ)-1:0] DivShiftAmt; + logic [`LOGNORMSHIFTSZ-1:0] DivShiftAmt; logic [`NORMSHIFTSZ-1:0] DivShiftIn; logic [`NE+1:0] Qe; logic DivByZero; logic DivResDenorm; - logic [`NE+1:0] DivDenormShift; + logic DivDenormShiftPos; // conversion signals logic [`CVTLEN+`NF:0] CvtShiftIn; // number to be shifted logic [1:0] CvtNegResMsbs; @@ -152,16 +152,16 @@ module postprocess ( .XZero, .IntToFp, .OutFmt, .CvtResUf, .CvtShiftIn); fmashiftcalc fmashiftcalc(.FmaSm, .Ze, .FmaPe, .FmaSCnt, .Fmt, .FmaKillProd, .NormSumExp, .FmaSe, .FmaSZero, .FmaPreResultDenorm, .FmaShiftAmt, .FmaShiftIn); - divshiftcalc divshiftcalc(.Fmt, .Sqrt, .DivQe, .DivQm, .DivEarlyTermShift, .DivResDenorm, .DivDenormShift, .DivShiftAmt, .DivShiftIn); + divshiftcalc divshiftcalc(.Fmt, .Sqrt, .DivQe, .DivQm, .DivResDenorm, .DivDenormShiftPos, .DivShiftAmt, .DivShiftIn); always_comb case(PostProcSel) 2'b10: begin // fma - ShiftAmt = {{$clog2(`NORMSHIFTSZ)-$clog2(3*`NF+7){1'b0}}, FmaShiftAmt}; + ShiftAmt = {{`LOGNORMSHIFTSZ-$clog2(3*`NF+7){1'b0}}, FmaShiftAmt}; ShiftIn = {FmaShiftIn, {`NORMSHIFTSZ-(3*`NF+8){1'b0}}}; end 2'b00: begin // cvt - ShiftAmt = {{$clog2(`NORMSHIFTSZ)-$clog2(`CVTLEN+1){1'b0}}, CvtShiftAmt}; + ShiftAmt = {{`LOGNORMSHIFTSZ-$clog2(`CVTLEN+1){1'b0}}, CvtShiftAmt}; ShiftIn = {CvtShiftIn, {`NORMSHIFTSZ-`CVTLEN-`NF-1{1'b0}}}; end 2'b01: begin //div @@ -174,7 +174,7 @@ module postprocess ( end end default: begin - ShiftAmt = {$clog2(`NORMSHIFTSZ){1'bx}}; + ShiftAmt = {`LOGNORMSHIFTSZ{1'bx}}; ShiftIn = {`NORMSHIFTSZ{1'bx}}; end endcase @@ -182,7 +182,7 @@ module postprocess ( normshift normshift (.ShiftIn, .ShiftAmt, .Shifted); shiftcorrection shiftcorrection(.FmaOp, .FmaPreResultDenorm, .NormSumExp, - .DivResDenorm, .DivDenormShift, .DivOp, .DivQe, + .DivResDenorm, .DivDenormShiftPos, .DivOp, .DivQe, .Qe, .FmaSZero, .Shifted, .FmaMe, .Mf); /////////////////////////////////////////////////////////////////////////////// diff --git a/pipelined/src/fpu/resultsign.sv b/pipelined/src/fpu/postproc/resultsign.sv similarity index 99% rename from pipelined/src/fpu/resultsign.sv rename to pipelined/src/fpu/postproc/resultsign.sv index 8d6dbb6e..cd7a096f 100644 --- a/pipelined/src/fpu/resultsign.sv +++ b/pipelined/src/fpu/postproc/resultsign.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// resultsign.sv // // Written: me@KatherineParry.com // Modified: 7/5/2022 diff --git a/pipelined/src/fpu/round.sv b/pipelined/src/fpu/postproc/round.sv similarity index 99% rename from pipelined/src/fpu/round.sv rename to pipelined/src/fpu/postproc/round.sv index d33d894a..e4450325 100644 --- a/pipelined/src/fpu/round.sv +++ b/pipelined/src/fpu/postproc/round.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// round.sv // // Written: me@KatherineParry.com // Modified: 7/5/2022 diff --git a/pipelined/src/fpu/roundsign.sv b/pipelined/src/fpu/postproc/roundsign.sv similarity index 98% rename from pipelined/src/fpu/roundsign.sv rename to pipelined/src/fpu/postproc/roundsign.sv index 62e882e6..1618f501 100644 --- a/pipelined/src/fpu/roundsign.sv +++ b/pipelined/src/fpu/postproc/roundsign.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// roundsign.sv // // Written: me@KatherineParry.com // Modified: 7/5/2022 diff --git a/pipelined/src/fpu/shiftcorrection.sv b/pipelined/src/fpu/postproc/shiftcorrection.sv similarity index 96% rename from pipelined/src/fpu/shiftcorrection.sv rename to pipelined/src/fpu/postproc/shiftcorrection.sv index 4839ba29..eca97bcf 100644 --- a/pipelined/src/fpu/shiftcorrection.sv +++ b/pipelined/src/fpu/postproc/shiftcorrection.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// shiftcorrection.sv // // Written: me@KatherineParry.com // Modified: 7/5/2022 @@ -34,7 +35,7 @@ module shiftcorrection( input logic DivOp, input logic DivResDenorm, input logic [`NE+1:0] DivQe, - input logic [`NE+1:0] DivDenormShift, + input logic DivDenormShiftPos, input logic [`NE+1:0] NormSumExp, // exponent of the normalized sum not taking into account denormal or zero results input logic FmaPreResultDenorm, // is the result denormalized - calculated before LZA corection input logic FmaSZero, @@ -66,5 +67,5 @@ module shiftcorrection( // the quotent is in the range [.5,2) if there is no early termination // if the quotent < 1 and not denormal then subtract 1 to account for the normalization shift - assign Qe = ((DivResDenorm)&~DivDenormShift[`NE+1]) ? (`NE+2)'(0) : DivQe - {(`NE+1)'(0), ~LZAPlus1}; + assign Qe = (DivResDenorm & DivDenormShiftPos) ? '0 : DivQe - {(`NE+1)'(0), ~LZAPlus1}; endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/specialcase.sv b/pipelined/src/fpu/postproc/specialcase.sv similarity index 99% rename from pipelined/src/fpu/specialcase.sv rename to pipelined/src/fpu/postproc/specialcase.sv index 41e75110..19d60ba7 100644 --- a/pipelined/src/fpu/specialcase.sv +++ b/pipelined/src/fpu/postproc/specialcase.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// specialcase.sv // // Written: me@KatherineParry.com // Modified: 7/5/2022 diff --git a/pipelined/src/fpu/qsel.sv b/pipelined/src/fpu/qsel.sv deleted file mode 100644 index 0a23b65e..00000000 --- a/pipelined/src/fpu/qsel.sv +++ /dev/null @@ -1,277 +0,0 @@ -/////////////////////////////////////////// -// srt.sv -// -// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu -// Modified:13 January 2022 -// -// Purpose: Combined Divide and Square Root Floating Point and Integer Unit -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module qsel2 ( // *** eventually just change to 4 bits - input logic [3:0] ps, pc, - output logic qp, qz, qn -); - - logic [3:0] p, g; - logic magnitude, sign, cout; - - // The quotient selection logic is presented for simplicity, not - // for efficiency. You can probably optimize your logic to - // select the proper divisor with less delay. - - // Qmient equations from EE371 lecture notes 13-20 - assign p = ps ^ pc; - assign g = ps & pc; - - //assign magnitude = ~(&p[2:0]); - assign cout = g[2] | (p[2] & (g[1] | p[1] & g[0])); - //assign sign = p[3] ^ cout; - assign magnitude = ~((ps[2]^pc[2]) & (ps[1]^pc[1]) & - (ps[0]^pc[0])); - assign sign = (ps[3]^pc[3])^ - (ps[2] & pc[2] | ((ps[2]^pc[2]) & - (ps[1]&pc[1] | ((ps[1]^pc[1]) & - (ps[0]&pc[0]))))); - - // Produce quotient = +1, 0, or -1 - assign qp = magnitude & ~sign; - assign qz = ~magnitude; - assign qn = magnitude & sign; -endmodule - -//////////////////////////////////// -// Adder Input Generation, Radix 2 // -//////////////////////////////////// -module fgen2 ( - input logic sp, sz, - input logic [`DIVb-1:0] C, - input logic [`DIVb:0] S, SM, - output logic [`DIVb+3:0] F -); - logic [`DIVb+3:0] FP, FN, FZ; - logic [`DIVb+3:0] SExt, SMExt, CExt; - - assign SExt = {3'b0, S}; - assign SMExt = {3'b0, SM}; - assign CExt = {4'hf, C}; // extend C from U0.k to Q4.k - - // Generate for both positive and negative bits - assign FP = ~(SExt << 1) & CExt; - assign FN = (SMExt << 1) | (CExt & ~(CExt << 2)); - assign FZ = '0; - - // Choose which adder input will be used - - always_comb - if (sp) F = FP; - else if (sz) F = FZ; - else F = FN; - -endmodule - -module qsel4 ( - input logic [`DIVN-2:0] D, - input logic [4:0] Smsbs, - input logic [`DIVb+3:0] WS, WC, - input logic Sqrt, j1, - output logic [3:0] q -); - logic [6:0] Wmsbs; - logic [7:0] PreWmsbs; - logic [2:0] Dmsbs, A; - - assign PreWmsbs = WC[`DIVb+3:`DIVb-4] + WS[`DIVb+3:`DIVb-4]; - assign Wmsbs = PreWmsbs[7:1]; - assign Dmsbs = D[`DIVN-2:`DIVN-4];//|{3{D[`DIVN-2]&Sqrt}}; - // D = 0001.xxx... - // Dmsbs = | | - // W = xxxx.xxx... - // Wmsbs = | | - - logic [3:0] QSel4[1023:0]; - - always_comb begin - integer a, w, i, w2; - for(a=0; a<8; a++) - for(w=0; w<128; w++)begin - i = a*128+w; - w2 = w-128*(w>=64); // convert to two's complement - case(a) - 0: if($signed(w2)>=$signed(12)) QSel4[i] = 4'b1000; - else if(w2>=4) QSel4[i] = 4'b0100; - else if(w2>=-4) QSel4[i] = 4'b0000; - else if(w2>=-13) QSel4[i] = 4'b0010; - else QSel4[i] = 4'b0001; - 1: if(w2>=14) QSel4[i] = 4'b1000; - else if(w2>=4) QSel4[i] = 4'b0100; - else if(w2>=-4) QSel4[i] = 4'b0000; - else if(w2>=-14) QSel4[i] = 4'b0010; - else QSel4[i] = 4'b0001; - 2: if(w2>=16) QSel4[i] = 4'b1000; - else if(w2>=4) QSel4[i] = 4'b0100; - else if(w2>=-6) QSel4[i] = 4'b0000; - else if(w2>=-16) QSel4[i] = 4'b0010; - else QSel4[i] = 4'b0001; - 3: if(w2>=16) QSel4[i] = 4'b1000; - else if(w2>=4) QSel4[i] = 4'b0100; - else if(w2>=-6) QSel4[i] = 4'b0000; - else if(w2>=-17) QSel4[i] = 4'b0010; - else QSel4[i] = 4'b0001; - 4: if(w2>=18) QSel4[i] = 4'b1000; - else if(w2>=6) QSel4[i] = 4'b0100; - else if(w2>=-6) QSel4[i] = 4'b0000; - else if(w2>=-18) QSel4[i] = 4'b0010; - else QSel4[i] = 4'b0001; - 5: if(w2>=20) QSel4[i] = 4'b1000; - else if(w2>=6) QSel4[i] = 4'b0100; - else if(w2>=-8) QSel4[i] = 4'b0000; - else if(w2>=-20) QSel4[i] = 4'b0010; - else QSel4[i] = 4'b0001; - 6: if(w2>=20) QSel4[i] = 4'b1000; - else if(w2>=8) QSel4[i] = 4'b0100; - else if(w2>=-8) QSel4[i] = 4'b0000; - else if(w2>=-22) QSel4[i] = 4'b0010; - else QSel4[i] = 4'b0001; - 7: if(w2>=24) QSel4[i] = 4'b1000; - else if(w2>=8) QSel4[i] = 4'b0100; - else if(w2>=-8) QSel4[i] = 4'b0000; - else if(w2>=-22) QSel4[i] = 4'b0010; - else QSel4[i] = 4'b0001; - endcase - end - end - always_comb - if (Sqrt) begin - if (j1) A = 3'b101; - else if (Smsbs == 5'b10000) A = 3'b111; - else A = Smsbs[2:0]; - end else A = Dmsbs; - assign q = QSel4[{A,Wmsbs}]; - -endmodule - -// qsel4old was working for divide -module qsel4old ( - input logic [`DIVN-2:0] D, - input logic [`DIVb+3:0] WS, WC, - input logic Sqrt, - output logic [3:0] q -); - logic [6:0] Wmsbs; - logic [7:0] PreWmsbs; - logic [2:0] Dmsbs; - assign PreWmsbs = WC[`DIVb+3:`DIVb-4] + WS[`DIVb+3:`DIVb-4]; - assign Wmsbs = PreWmsbs[7:1]; - assign Dmsbs = D[`DIVN-2:`DIVN-4];//|{3{D[`DIVN-2]&Sqrt}}; - // D = 0001.xxx... - // Dmsbs = | | - // W = xxxx.xxx... - // Wmsbs = | | - - logic [3:0] QSel4[1023:0]; - - always_comb begin - integer d, w, i, w2; - for(d=0; d<8; d++) - for(w=0; w<128; w++)begin - i = d*128+w; - w2 = w-128*(w>=64); // convert to two's complement - case(d) - 0: if($signed(w2)>=$signed(12)) QSel4[i] = 4'b1000; - else if(w2>=4) QSel4[i] = 4'b0100; - else if(w2>=-4) QSel4[i] = 4'b0000; - else if(w2>=-13) QSel4[i] = 4'b0010; - else QSel4[i] = 4'b0001; - 1: if(w2>=14) QSel4[i] = 4'b1000; - else if(w2>=4) QSel4[i] = 4'b0100; - else if(w2>=-5) QSel4[i] = 4'b0000; // was -6 - else if(~Sqrt&(w2>=-15)) QSel4[i] = 4'b0010; // divide case - else if( Sqrt&(w2>=-14)) QSel4[i] = 4'b0010; // sqrt case - else QSel4[i] = 4'b0001; - 2: if(w2>=15) QSel4[i] = 4'b1000; - else if(w2>=4) QSel4[i] = 4'b0100; - else if(w2>=-6) QSel4[i] = 4'b0000; - else if(w2>=-16) QSel4[i] = 4'b0010; - else QSel4[i] = 4'b0001; - 3: if(w2>=16) QSel4[i] = 4'b1000; - else if(w2>=4) QSel4[i] = 4'b0100; - else if(w2>=-6) QSel4[i] = 4'b0000; - else if(w2>=-17) QSel4[i] = 4'b0010; // was -18 - else QSel4[i] = 4'b0001; - 4: if(w2>=18) QSel4[i] = 4'b1000; - else if(w2>=6) QSel4[i] = 4'b0100; - else if(w2>=-6) QSel4[i] = 4'b0000; // was -8 - else if(~Sqrt&(w2>=-20)) QSel4[i] = 4'b0010; // divide case - else if( Sqrt&(w2>=-18)) QSel4[i] = 4'b0010; // sqrt case - else QSel4[i] = 4'b0001; - 5: if(w2>=20) QSel4[i] = 4'b1000; - else if(w2>=6) QSel4[i] = 4'b0100; - else if(w2>=-8) QSel4[i] = 4'b0000; - else if(w2>=-20) QSel4[i] = 4'b0010; - else QSel4[i] = 4'b0001; - 6: if(w2>=20) QSel4[i] = 4'b1000; - else if(w2>=8) QSel4[i] = 4'b0100; - else if(w2>=-8) QSel4[i] = 4'b0000; - else if(w2>=-22) QSel4[i] = 4'b0010; - else QSel4[i] = 4'b0001; - 7: if(w2>=22) QSel4[i] = 4'b1000; // was 24 - else if(w2>=8) QSel4[i] = 4'b0100; - else if(w2>=-8) QSel4[i] = 4'b0000; - else if(w2>=-23) QSel4[i] = 4'b0010; // was -24 ***use -22 - else QSel4[i] = 4'b0001; - endcase - end - end - assign q = QSel4[{Dmsbs,Wmsbs}]; - -endmodule - -//////////////////////////////////// -// Adder Input Generation, Radix 4 // -//////////////////////////////////// -module fgen4 ( - input logic [3:0] s, - input logic [`DIVb+3:0] C, S, SM, - output logic [`DIVb+3:0] F -); - logic [`DIVb+3:0] F2, F1, F0, FN1, FN2; - - // Generate for both positive and negative bits - assign F2 = (~S << 2) & (C << 2); - assign F1 = ~(S << 1) & C; - assign F0 = '0; - assign FN1 = (SM << 1) | (C & ~(C << 3)); - assign FN2 = (SM << 2) | ((C << 2)&~(C << 4)); - - // Choose which adder input will be used - - always_comb - if (s[3]) F = F2; - else if (s[2]) F = F1; - else if (s[1]) F = FN1; - else if (s[0]) F = FN2; - else F = F0; -endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/unpack.sv b/pipelined/src/fpu/unpack.sv index 4053cba1..8444a2c6 100644 --- a/pipelined/src/fpu/unpack.sv +++ b/pipelined/src/fpu/unpack.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// unpack.sv // // Written: me@KatherineParry.com // Modified: 7/5/2022 diff --git a/pipelined/src/fpu/unpackinput.sv b/pipelined/src/fpu/unpackinput.sv index 4e43768c..bf524698 100644 --- a/pipelined/src/fpu/unpackinput.sv +++ b/pipelined/src/fpu/unpackinput.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// unpackinput.sv // // Written: me@KatherineParry.com // Modified: 7/5/2022 diff --git a/pipelined/src/uncore/uartPC16550D.sv b/pipelined/src/uncore/uartPC16550D.sv index a55350c6..c0513ac6 100644 --- a/pipelined/src/uncore/uartPC16550D.sv +++ b/pipelined/src/uncore/uartPC16550D.sv @@ -82,7 +82,7 @@ module uartPC16550D( logic DLAB; // Divisor Latch Access Bit (LCR bit 7) // Baud and rx/tx timing - logic baudpulse, txbaudpulse, rxbaudpulse; // high one system clk cycle each baud/16 period + (* mark_debug = "true" *) logic baudpulse, txbaudpulse, rxbaudpulse; // high one system clk cycle each baud/16 period logic [16+`UART_PRESCALE-1:0] baudcount; logic [3:0] rxoversampledcnt, txoversampledcnt; // count oversampled-by-16 logic [3:0] rxbitsreceived, txbitssent; @@ -90,8 +90,8 @@ module uartPC16550D( // shift registrs and FIFOs logic [9:0] rxshiftreg; - logic [10:0] rxfifo[15:0]; - logic [7:0] txfifo[15:0]; + (* mark_debug = "true" *) logic [10:0] rxfifo[15:0]; + (* mark_debug = "true" *) logic [7:0] txfifo[15:0]; logic [4:0] rxfifotailunwrapped; (* mark_debug = "true" *) logic [3:0] rxfifohead, rxfifotail, txfifohead, txfifotail, rxfifotriggerlevel; (* mark_debug = "true" *) logic [3:0] rxfifoentries, txfifoentries; @@ -99,7 +99,7 @@ module uartPC16550D( // receive data (* mark_debug = "true" *) logic [10:0] RXBR; - logic [6:0] rxtimeoutcnt; + (* mark_debug = "true" *) logic [6:0] rxtimeoutcnt; logic rxcentered; logic rxparity, rxparitybit, rxstopbit; (* mark_debug = "true" *) logic rxparityerr, rxoverrunerr, rxframingerr, rxbreak, rxfifohaserr; @@ -107,16 +107,16 @@ module uartPC16550D( (* mark_debug = "true" *) logic rxfifoempty, rxfifotriggered, rxfifotimeout; logic rxfifodmaready; logic [8:0] rxdata9; - logic [7:0] rxdata; - logic [15:0] RXerrbit, rxfullbit; - logic [31:0] rxfullbitunwrapped; + (* mark_debug = "true" *) logic [7:0] rxdata; + (* mark_debug = "true" *) logic [15:0] RXerrbit, rxfullbit; + (* mark_debug = "true" *) logic [31:0] rxfullbitunwrapped; // transmit data logic [7:0] TXHR, nexttxdata; - logic [11:0] txdata, txsr; - logic txnextbit, txhrfull, txsrfull; + (* mark_debug = "true" *) logic [11:0] txdata, txsr; + (* mark_debug = "true" *) logic txnextbit, txhrfull, txsrfull; logic txparity; - logic txfifoempty, txfifofull, txfifodmaready; + (* mark_debug = "true" *) logic txfifoempty, txfifofull, txfifodmaready; // control signals (* mark_debug = "true" *) logic fifoenabled, fifodmamodesel, evenparitysel; @@ -154,7 +154,7 @@ module uartPC16550D( //DLL <= #1 8'd38; // 35Mhz //DLL <= #1 8'd11; // 10 Mhz //DLL <= #1 8'd33; // 30 Mhz - DLL <= #1 8'd8; // 30 Mhz 230400 + DLL <= #1 8'd11; // 30 Mhz 230400 DLM <= #1 8'b0; end else begin DLL <= #1 8'd1; // this cannot be zero with DLM also zer0. @@ -178,7 +178,7 @@ module uartPC16550D( // freq /baud / 16 = div //3'b000: if (DLAB) DLL <= #1 8'd38; //else TXHR <= #1 Din; // TX handled in TX register/FIFO section //3'b000: if (DLAB) DLL <= #1 8'd11; //else TXHR <= #1 Din; // TX handled in - 3'b000: if (DLAB) DLL <= #1 8'd8; //else TXHR <= #1 Din; // TX handled in + 3'b000: if (DLAB) DLL <= #1 8'd11; //else TXHR <= #1 Din; // TX handled in 3'b001: if (DLAB) DLM <= #1 8'b0; else IER <= #1 Din[3:0]; 3'b010: FCR <= #1 {Din[7:6], 2'b0, Din[3], 2'b0, Din[0]}; // Write only FIFO Control Register; 4:5 reserved and 2:1 self-clearing 3'b011: LCR <= #1 Din; @@ -275,7 +275,7 @@ module uartPC16550D( rxstate <= #1 UART_ACTIVE; rxoversampledcnt <= #1 0; rxbitsreceived <= #1 0; - rxtimeoutcnt <= #1 0; // reset timeout when new character is arriving + if (~rxfifotimeout) rxtimeoutcnt <= #1 0; // reset timeout when new character is arriving. Jacob Pease: Only if the timeout was not already reached. p.16 PC16550D.pdf end else if (rxbaudpulse & (rxstate == UART_ACTIVE)) begin rxoversampledcnt <= #1 rxoversampledcnt + 1; // 16x oversampled counter if (rxcentered) rxbitsreceived <= #1 rxbitsreceived + 1; @@ -357,8 +357,8 @@ module uartPC16550D( (rxfifohead + 16 - rxfifotail); // verilator lint_on WIDTH assign rxfifotriggered = rxfifoentries >= rxfifotriggerlevel; - //assign rxfifotimeout = rxtimeoutcnt[6]; // time out after 4 character periods; *** probably not right yet - assign rxfifotimeout = 0; // disabled pending fix + assign rxfifotimeout = rxtimeoutcnt[6]; // time out after 4 character periods; *** probably not right yet + //assign rxfifotimeout = 0; // disabled pending fix // detect any errors in rx fifo // although rxfullbit looks like a combinational loop, in one bit rxfifotail == i and breaks the loop diff --git a/pipelined/testbench/testbench-fp.sv b/pipelined/testbench/testbench-fp.sv index 59331179..9f7df893 100644 --- a/pipelined/testbench/testbench-fp.sv +++ b/pipelined/testbench/testbench-fp.sv @@ -80,9 +80,8 @@ module testbenchfp; logic CvtResSgnE; logic [`NE:0] CvtCalcExpE; // the calculated expoent logic [`LOGCVTLEN-1:0] CvtShiftAmtE; // how much to shift by - logic [`DIVb-(`RADIX/4):0] Quot; + logic [`DIVb:0] Quot; logic CvtResDenormUfE; - logic [`DURLEN-1:0] EarlyTermShift; logic DivStart, DivBusy; logic reset = 1'b0; logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt; @@ -575,13 +574,20 @@ module testbenchfp; end if (TEST === "div" | TEST === "all") begin // if division is being tested // add the correct tests/op-ctrls/unit/fmt to their lists - Tests = {Tests, f16div}; + Tests = {f16div, Tests}; + OpCtrl = {`DIV_OPCTRL, OpCtrl}; + WriteInt = {1'b0, WriteInt}; + for(int i = 0; i<5; i++) begin + Unit = {`DIVUNIT, Unit}; + Fmt = {2'b10, Fmt}; + end + /* Tests = {Tests, f16div}; OpCtrl = {OpCtrl, `DIV_OPCTRL}; WriteInt = {WriteInt, 1'b0}; for(int i = 0; i<5; i++) begin Unit = {Unit, `DIVUNIT}; Fmt = {Fmt, 2'b10}; - end + end */ end if (TEST === "sqrt" | TEST === "all") begin // if sqrt is being tested // add the correct tests/op-ctrls/unit/fmt to their lists @@ -694,7 +700,7 @@ module testbenchfp; .XInf(XInf), .YInf(YInf), .ZInf(ZInf), .CvtCs(CvtResSgnE), .ToInt(WriteIntVal), .XSNaN(XSNaN), .YSNaN(YSNaN), .ZSNaN(ZSNaN), .CvtLzcIn(CvtLzcInE), .IntZero, .FmaKillProd(KillProd), .FmaZmS(ZmSticky), .FmaPe(Pe), .DivDone, .FmaSe(Se), - .FmaSm(Sm), .FmaNegSum(NegSum), .FmaInvA(InvA), .FmaSCnt(SCnt), .DivEarlyTermShift(EarlyTermShift), .FmaAs(As), .FmaPs(Ps), .Fmt(ModFmt), .Frm(FrmVal), + .FmaSm(Sm), .FmaNegSum(NegSum), .FmaInvA(InvA), .FmaSCnt(SCnt), .FmaAs(As), .FmaPs(Ps), .Fmt(ModFmt), .Frm(FrmVal), .PostProcFlg(Flg), .PostProcRes(FpRes), .FCvtIntRes(IntRes)); if (TEST === "cvtfp" | TEST === "cvtint" | TEST === "all") begin : fcvt @@ -712,7 +718,7 @@ module testbenchfp; fdivsqrt fdivsqrt(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym), .XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]), .XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero), .XNaNE(XNaN), .YNaNE(YNaN), .DivStartE(DivStart), .StallE(1'b0), .StallM(1'b0), .DivSM(DivSticky), .DivBusy, .QeM(DivCalcExp), - .EarlyTermShiftM(EarlyTermShift), .QmM(Quot), .DivDone); + .QmM(Quot), .DivDone); end assign CmpFlg[3:0] = 0; @@ -801,6 +807,8 @@ always_comb begin endcase end + logic ResMatch, FlagMatch, CheckNow; + // check results on falling edge of clk always @(negedge clk) begin @@ -870,7 +878,11 @@ always @(negedge clk) begin // check if result is correct // - wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage) // if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&~((DivBusy===1'b1)|DivStart)&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin - if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&(DivDone | (TEST != "sqrt" & TEST != "div"))&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin + assign ResMatch = (Res === Ans | NaNGood | NaNGood === 1'bx); + assign FlagMatch = (ResFlg === AnsFlg | AnsFlg === 5'bx); + assign CheckNow = (DivDone | (TEST != "sqrt" & TEST != "div"))&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT); + if(~(ResMatch & FlagMatch) & CheckNow) begin +// if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&(DivDone | (TEST != "sqrt" & TEST != "div"))&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin errors += 1; $display("Error in %s", Tests[TestNum]); $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);