From e98dd420bcf4e4d815d9e1546077fc6bea97c647 Mon Sep 17 00:00:00 2001
From: bbracker <bbracker@hmc.edu>
Date: Thu, 25 Mar 2021 00:10:44 -0400
Subject: [PATCH] future work comment about suspicious-looking verilog in
 csri.sv

---
 wally-pipelined/src/privileged/csri.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/wally-pipelined/src/privileged/csri.sv b/wally-pipelined/src/privileged/csri.sv
index ee84c222..488c6ba4 100644
--- a/wally-pipelined/src/privileged/csri.sv
+++ b/wally-pipelined/src/privileged/csri.sv
@@ -49,7 +49,7 @@ module csri #(parameter
   // assumes no N-mode user interrupts
 
   always_comb begin
-    IntInM     = 0;
+    IntInM     = 0; // *** does this really work
     IntInM[11] = ExtIntM & ~MIDELEG_REGW[9];   // MEIP
     IntInM[9]  = ExtIntM &  MIDELEG_REGW[9];   // SEIP
     IntInM[7]  = TimerIntM & ~MIDELEG_REGW[5]; // MTIP