diff --git a/fpga/constraints/constraints.xdc b/fpga/constraints/constraints.xdc
new file mode 100644
index 00000000..746073ba
--- /dev/null
+++ b/fpga/constraints/constraints.xdc
@@ -0,0 +1,286 @@
+# The main clocks are all autogenerated by the Xilinx IP
+# mmcm_clkout1 is the 22Mhz clock from the DDR4 IP used to drive wally and the AHBLite Bus.
+# mmcm_clkout0 is the clock output of the DDR4 memory interface / 4.
+# This clock is not used by wally or the AHBLite Bus. However it is used by the AXI BUS on the DD4 IP.
+
+# generate 1 clock for the slow speed SD Card hardware. However we need to time at the mmcm_clkout1
+# clock speed.
+
+#create_generated_clock -name r_fd_Q -source [get_pins wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/toggle_flip_flop/i_CLK] -divide_by 50 [get_pins wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/toggle_flip_flop/r_fd_Q]
+
+#create_clock -period 4.000 [get_ports default_250mhz_clk1_0_p]
+
+
+create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 [get_pins wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
+
+
+
+#create_generated_clock -name mmcm_clkout1_Gen -source [get_pins wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -divide_by 1 -add -master_clock mmcm_clkout1 [get_pins wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
+
+#create_generated_clock -name CLKDiv64_Gen -source [get_pins wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I1] -divide_by 1 -add -master_clock mmcm_clkout1_Gen [get_pins wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
+
+
+
+#create_generated_clock -name mmcm_clkout1_Gen_slow -source [get_pins wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -divide_by 8 -add -master_clock mmcm_clkout1 [get_pins wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
+
+#create_generated_clock -name CLKDiv64_Gen_slow -source [get_pins wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I1] -divide_by 8 -add -master_clock mmcm_clkout1_Gen_slow [get_pins wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
+
+#set_clock_groups -logically_exclusive -group [get_clocks -include_generated_clocks mmcm_clkout1_Gen] -group [get_clocks -include_generated_clocks CLKDiv64_Gen]
+#set_clock_groups -logically_exclusive -group [get_clocks -include_generated_clocks mmcm_clkout1_Gen] -group [get_clocks -include_generated_clocks CLKDiv64_Gen_slow]
+
+
+##### GPI ####
+set_property PACKAGE_PIN BB24 [get_ports {GPI[0]}]
+set_property PACKAGE_PIN BF22 [get_ports {GPI[1]}]
+set_property PACKAGE_PIN BD23 [get_ports {GPI[2]}]
+set_property PACKAGE_PIN BE23 [get_ports {GPI[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {GPI[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {GPI[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {GPI[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {GPI[0]}]
+set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports {GPI[*]}]
+set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports {GPI[*]}]
+set_max_delay -from [get_ports {GPI[*]}] 10.000
+
+##### GPO ####
+set_property PACKAGE_PIN AT32 [get_ports {GPO[0]}]
+set_property PACKAGE_PIN AV34 [get_ports {GPO[1]}]
+set_property PACKAGE_PIN AY30 [get_ports {GPO[2]}]
+set_property PACKAGE_PIN BF32 [get_ports {GPO[4]}]
+set_property PACKAGE_PIN BB32 [get_ports {GPO[3]}]
+set_property IOSTANDARD LVCMOS12 [get_ports {GPO[4]}]
+set_property IOSTANDARD LVCMOS12 [get_ports {GPO[3]}]
+set_property IOSTANDARD LVCMOS12 [get_ports {GPO[2]}]
+set_property IOSTANDARD LVCMOS12 [get_ports {GPO[1]}]
+set_property IOSTANDARD LVCMOS12 [get_ports {GPO[0]}]
+set_max_delay -to [get_ports {GPO[*]}] 10.000
+set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {GPO[*]}]
+set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {GPO[*]}]
+
+
+##### UART #####
+set_property PACKAGE_PIN AW25 [get_ports UARTSin]
+set_property PACKAGE_PIN BB21 [get_ports UARTSout]
+set_max_delay -from [get_ports UARTSin] 10.000
+set_max_delay -to [get_ports UARTSout] 10.000
+set_property IOSTANDARD LVCMOS18 [get_ports UARTSin]
+set_property IOSTANDARD LVCMOS18 [get_ports UARTSout]
+set_property DRIVE 6 [get_ports UARTSout]
+set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports UARTSin]
+set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports UARTSin]
+set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports UARTSout]
+set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports UARTSout]
+
+
+##### reset #####
+set_input_delay -clock [get_clocks default_250mhz_clk1_0_p] -min -add_delay 2.000 [get_ports reset]
+set_input_delay -clock [get_clocks default_250mhz_clk1_0_p] -max -add_delay 2.000 [get_ports reset]
+set_input_delay -clock [get_clocks mmcm_clkout0] -min -add_delay 0.000 [get_ports reset]
+set_input_delay -clock [get_clocks mmcm_clkout0] -max -add_delay 0.000 [get_ports reset]
+set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports reset]
+set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports reset]
+set_max_delay -from [get_ports reset] 15.000
+set_false_path -from [get_ports reset]
+
+
+
+##### cpu_reset #####
+set_property PACKAGE_PIN AV36 [get_ports {cpu_reset}]
+set_property IOSTANDARD LVCMOS12 [get_ports {cpu_reset}]
+set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {cpu_reset}]
+set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {cpu_reset}]
+
+
+##### calib #####
+set_property PACKAGE_PIN BA37 [get_ports calib]
+set_property IOSTANDARD LVCMOS12 [get_ports calib]
+set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports calib]
+set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports calib]
+set_max_delay -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_ports calib] 50.000
+
+
+##### ahblite_resetn #####
+set_property PACKAGE_PIN AU37 [get_ports {ahblite_resetn}]
+set_property IOSTANDARD LVCMOS12 [get_ports {ahblite_resetn}]
+set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {ahblite_resetn}]
+set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {ahblite_resetn}]
+
+
+##### south_rst #####
+set_property PACKAGE_PIN BE22 [get_ports south_rst]
+set_property IOSTANDARD LVCMOS18 [get_ports south_rst]
+set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports south_rst]
+set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports south_rst]
+
+
+##### SD Card I/O #####
+set_property PACKAGE_PIN AY14 [get_ports {SDCDat[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[0]}]
+set_property PACKAGE_PIN AU16 [get_ports {SDCDat[2]}]
+set_property PACKAGE_PIN AV16 [get_ports {SDCDat[1]}]
+set_property PACKAGE_PIN AW15 [get_ports {SDCDat[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports SDCCLK]
+set_property IOSTANDARD LVCMOS18 [get_ports {SDCCmd}]
+set_property PACKAGE_PIN AV15 [get_ports SDCCLK]
+set_property PACKAGE_PIN AY15 [get_ports {SDCCmd}]
+set_property PULLUP true [get_ports {SDCDat[3]}]
+set_property PULLUP true [get_ports {SDCDat[2]}]
+set_property PULLUP true [get_ports {SDCDat[1]}]
+set_property PULLUP true [get_ports {SDCDat[0]}]
+set_property PULLUP true [get_ports {SDCCmd}]
+
+
+set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCDat[*]}]
+set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 21.000 [get_ports {SDCDat[*]}]
+
+set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCCmd}]
+set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 14.000 [get_ports {SDCCmd}]
+
+
+set_output_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.000 [get_ports {SDCCmd}]
+set_output_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 6.000 [get_ports {SDCCmd}]
+
+set_output_delay -clock [get_clocks CLKDiv64_Gen] 0.000 [get_ports SDCCLK]
+
+
+
+set_property DCI_CASCADE {64} [get_iobanks 65]
+set_property INTERNAL_VREF 0.9 [get_iobanks 65]
+
+
+set_property PACKAGE_PIN E13 [get_ports c0_ddr4_act_n]
+set_property PACKAGE_PIN D14 [get_ports {c0_ddr4_adr[0]}]
+set_property PACKAGE_PIN C12 [get_ports {c0_ddr4_adr[10]}]
+set_property PACKAGE_PIN B13 [get_ports {c0_ddr4_adr[11]}]
+set_property PACKAGE_PIN C13 [get_ports {c0_ddr4_adr[12]}]
+set_property PACKAGE_PIN D15 [get_ports {c0_ddr4_adr[13]}]
+set_property PACKAGE_PIN H14 [get_ports {c0_ddr4_adr[14]}]
+set_property PACKAGE_PIN H15 [get_ports {c0_ddr4_adr[15]}]
+set_property PACKAGE_PIN F15 [get_ports {c0_ddr4_adr[16]}]
+set_property PACKAGE_PIN B15 [get_ports {c0_ddr4_adr[1]}]
+set_property PACKAGE_PIN B16 [get_ports {c0_ddr4_adr[2]}]
+set_property PACKAGE_PIN C14 [get_ports {c0_ddr4_adr[3]}]
+set_property PACKAGE_PIN C15 [get_ports {c0_ddr4_adr[4]}]
+set_property PACKAGE_PIN A13 [get_ports {c0_ddr4_adr[5]}]
+set_property PACKAGE_PIN A14 [get_ports {c0_ddr4_adr[6]}]
+set_property PACKAGE_PIN A15 [get_ports {c0_ddr4_adr[7]}]
+set_property PACKAGE_PIN A16 [get_ports {c0_ddr4_adr[8]}]
+set_property PACKAGE_PIN B12 [get_ports {c0_ddr4_adr[9]}]
+set_property PACKAGE_PIN G15 [get_ports {c0_ddr4_ba[0]}]
+set_property PACKAGE_PIN G13 [get_ports {c0_ddr4_ba[1]}]
+set_property PACKAGE_PIN H13 [get_ports {c0_ddr4_bg[0]}]
+set_property PACKAGE_PIN F14 [get_ports {c0_ddr4_ck_t[0]}]
+set_property PACKAGE_PIN E14 [get_ports {c0_ddr4_ck_c[0]}]
+set_property PACKAGE_PIN A10 [get_ports {c0_ddr4_cke[0]}]
+set_property PACKAGE_PIN F13 [get_ports {c0_ddr4_cs_n[0]}]
+set_property PACKAGE_PIN F11 [get_ports {c0_ddr4_dq[0]}]
+set_property PACKAGE_PIN M18 [get_ports {c0_ddr4_dq[10]}]
+set_property PACKAGE_PIN M17 [get_ports {c0_ddr4_dq[11]}]
+set_property PACKAGE_PIN N19 [get_ports {c0_ddr4_dq[12]}]
+set_property PACKAGE_PIN N18 [get_ports {c0_ddr4_dq[13]}]
+set_property PACKAGE_PIN N17 [get_ports {c0_ddr4_dq[14]}]
+set_property PACKAGE_PIN M16 [get_ports {c0_ddr4_dq[15]}]
+set_property PACKAGE_PIN L16 [get_ports {c0_ddr4_dq[16]}]
+set_property PACKAGE_PIN K16 [get_ports {c0_ddr4_dq[17]}]
+set_property PACKAGE_PIN L18 [get_ports {c0_ddr4_dq[18]}]
+set_property PACKAGE_PIN K18 [get_ports {c0_ddr4_dq[19]}]
+set_property PACKAGE_PIN E11 [get_ports {c0_ddr4_dq[1]}]
+set_property PACKAGE_PIN J17 [get_ports {c0_ddr4_dq[20]}]
+set_property PACKAGE_PIN H17 [get_ports {c0_ddr4_dq[21]}]
+set_property PACKAGE_PIN H19 [get_ports {c0_ddr4_dq[22]}]
+set_property PACKAGE_PIN H18 [get_ports {c0_ddr4_dq[23]}]
+set_property PACKAGE_PIN F19 [get_ports {c0_ddr4_dq[24]}]
+set_property PACKAGE_PIN F18 [get_ports {c0_ddr4_dq[25]}]
+set_property PACKAGE_PIN E19 [get_ports {c0_ddr4_dq[26]}]
+set_property PACKAGE_PIN E18 [get_ports {c0_ddr4_dq[27]}]
+set_property PACKAGE_PIN G20 [get_ports {c0_ddr4_dq[28]}]
+set_property PACKAGE_PIN F20 [get_ports {c0_ddr4_dq[29]}]
+set_property PACKAGE_PIN F10 [get_ports {c0_ddr4_dq[2]}]
+set_property PACKAGE_PIN E17 [get_ports {c0_ddr4_dq[30]}]
+set_property PACKAGE_PIN D16 [get_ports {c0_ddr4_dq[31]}]
+set_property PACKAGE_PIN D17 [get_ports {c0_ddr4_dq[32]}]
+set_property PACKAGE_PIN C17 [get_ports {c0_ddr4_dq[33]}]
+set_property PACKAGE_PIN C19 [get_ports {c0_ddr4_dq[34]}]
+set_property PACKAGE_PIN C18 [get_ports {c0_ddr4_dq[35]}]
+set_property PACKAGE_PIN D20 [get_ports {c0_ddr4_dq[36]}]
+set_property PACKAGE_PIN D19 [get_ports {c0_ddr4_dq[37]}]
+set_property PACKAGE_PIN C20 [get_ports {c0_ddr4_dq[38]}]
+set_property PACKAGE_PIN B20 [get_ports {c0_ddr4_dq[39]}]
+set_property PACKAGE_PIN F9 [get_ports {c0_ddr4_dq[3]}]
+set_property PACKAGE_PIN N23 [get_ports {c0_ddr4_dq[40]}]
+set_property PACKAGE_PIN M23 [get_ports {c0_ddr4_dq[41]}]
+set_property PACKAGE_PIN R21 [get_ports {c0_ddr4_dq[42]}]
+set_property PACKAGE_PIN P21 [get_ports {c0_ddr4_dq[43]}]
+set_property PACKAGE_PIN R22 [get_ports {c0_ddr4_dq[44]}]
+set_property PACKAGE_PIN P22 [get_ports {c0_ddr4_dq[45]}]
+set_property PACKAGE_PIN T23 [get_ports {c0_ddr4_dq[46]}]
+set_property PACKAGE_PIN R23 [get_ports {c0_ddr4_dq[47]}]
+set_property PACKAGE_PIN K24 [get_ports {c0_ddr4_dq[48]}]
+set_property PACKAGE_PIN J24 [get_ports {c0_ddr4_dq[49]}]
+set_property PACKAGE_PIN H12 [get_ports {c0_ddr4_dq[4]}]
+set_property PACKAGE_PIN M21 [get_ports {c0_ddr4_dq[50]}]
+set_property PACKAGE_PIN L21 [get_ports {c0_ddr4_dq[51]}]
+set_property PACKAGE_PIN K21 [get_ports {c0_ddr4_dq[52]}]
+set_property PACKAGE_PIN J21 [get_ports {c0_ddr4_dq[53]}]
+set_property PACKAGE_PIN K22 [get_ports {c0_ddr4_dq[54]}]
+set_property PACKAGE_PIN J22 [get_ports {c0_ddr4_dq[55]}]
+set_property PACKAGE_PIN H23 [get_ports {c0_ddr4_dq[56]}]
+set_property PACKAGE_PIN H22 [get_ports {c0_ddr4_dq[57]}]
+set_property PACKAGE_PIN E23 [get_ports {c0_ddr4_dq[58]}]
+set_property PACKAGE_PIN E22 [get_ports {c0_ddr4_dq[59]}]
+set_property PACKAGE_PIN G12 [get_ports {c0_ddr4_dq[5]}]
+set_property PACKAGE_PIN F21 [get_ports {c0_ddr4_dq[60]}]
+set_property PACKAGE_PIN E21 [get_ports {c0_ddr4_dq[61]}]
+set_property PACKAGE_PIN F24 [get_ports {c0_ddr4_dq[62]}]
+set_property PACKAGE_PIN F23 [get_ports {c0_ddr4_dq[63]}]
+set_property PACKAGE_PIN E9 [get_ports {c0_ddr4_dq[6]}]
+set_property PACKAGE_PIN D9 [get_ports {c0_ddr4_dq[7]}]
+set_property PACKAGE_PIN R19 [get_ports {c0_ddr4_dq[8]}]
+set_property PACKAGE_PIN P19 [get_ports {c0_ddr4_dq[9]}]
+set_property PACKAGE_PIN D11 [get_ports {c0_ddr4_dqs_t[0]}]
+set_property PACKAGE_PIN D10 [get_ports {c0_ddr4_dqs_c[0]}]
+set_property PACKAGE_PIN P17 [get_ports {c0_ddr4_dqs_t[1]}]
+set_property PACKAGE_PIN P16 [get_ports {c0_ddr4_dqs_c[1]}]
+set_property PACKAGE_PIN K19 [get_ports {c0_ddr4_dqs_t[2]}]
+set_property PACKAGE_PIN J19 [get_ports {c0_ddr4_dqs_c[2]}]
+set_property PACKAGE_PIN F16 [get_ports {c0_ddr4_dqs_t[3]}]
+set_property PACKAGE_PIN E16 [get_ports {c0_ddr4_dqs_c[3]}]
+set_property PACKAGE_PIN A19 [get_ports {c0_ddr4_dqs_t[4]}]
+set_property PACKAGE_PIN A18 [get_ports {c0_ddr4_dqs_c[4]}]
+set_property PACKAGE_PIN N22 [get_ports {c0_ddr4_dqs_t[5]}]
+set_property PACKAGE_PIN M22 [get_ports {c0_ddr4_dqs_c[5]}]
+set_property PACKAGE_PIN M20 [get_ports {c0_ddr4_dqs_t[6]}]
+set_property PACKAGE_PIN L20 [get_ports {c0_ddr4_dqs_c[6]}]
+set_property PACKAGE_PIN H24 [get_ports {c0_ddr4_dqs_t[7]}]
+set_property PACKAGE_PIN G23 [get_ports {c0_ddr4_dqs_c[7]}]
+set_property PACKAGE_PIN C8 [get_ports {c0_ddr4_odt[0]}]
+set_property PACKAGE_PIN N20 [get_ports c0_ddr4_reset_n]
+
+
+set_property PACKAGE_PIN G11 [get_ports {c0_ddr4_dm_dbi_n[0]}]
+set_property PACKAGE_PIN R18 [get_ports {c0_ddr4_dm_dbi_n[1]}]
+set_property PACKAGE_PIN K17 [get_ports {c0_ddr4_dm_dbi_n[2]}]
+set_property PACKAGE_PIN G18 [get_ports {c0_ddr4_dm_dbi_n[3]}]
+set_property PACKAGE_PIN B18 [get_ports {c0_ddr4_dm_dbi_n[4]}]
+set_property PACKAGE_PIN P20 [get_ports {c0_ddr4_dm_dbi_n[5]}]
+set_property PACKAGE_PIN L23 [get_ports {c0_ddr4_dm_dbi_n[6]}]
+set_property PACKAGE_PIN G22 [get_ports {c0_ddr4_dm_dbi_n[7]}]
+
+
+
+
+
+set_max_delay -datapath_only -from [get_pins wrapper_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins wrapper_i/proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000
+
+
+set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n]
+set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports c0_ddr4_reset_n]
+
+
+
+set_max_delay -from [get_pins {xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C}] -to [get_ports c0_ddr4_reset_n] 50.000
+
+
diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl
new file mode 100644
index 00000000..a61a7a81
--- /dev/null
+++ b/fpga/generator/wally.tcl
@@ -0,0 +1,76 @@
+# start by reading in all the IP blocks generated by vivado
+
+set partNumber xcvu9p-flga2104-2L-e
+set boardName  xilinx.com:vcu118:part0:2.4
+
+set ipName WallyFPGA
+
+create_project $ipName . -force -part $partNumber
+set_property board_part $boardName [current_project]
+
+read_ip IP/xlnx_proc_sys_reset.srcs/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xci
+read_ip IP/xlnx_ahblite_axi_bridge.srcs/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge.xci
+read_ip IP/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter.xci
+read_ip IP/xlnx_ddr4.srcs/sources_1/ip/xlnx_ddr4/xlnx_ddr4.xci
+
+
+read_verilog -sv [glob -type f ../../wally-pipelined/src/*/*.sv ../../wally-pipelined/src/*/*/*.sv]
+read_verilog  {../src/fpgaTop.v}
+
+set_property include_dirs {../../wally-pipelined/config/fpga ../../wally-pipelined/config/shared} [current_fileset]
+
+# contrainsts generated by the IP blocks
+add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_1/par/xlnx_ddr4_phy_ooc.xdc
+add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_2/bd_1ba7_ilmb_0.xdc
+add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_10/bd_1ba7_iomodule_0_0_board.xdc
+add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0_board.xdc
+add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0.xdc
+add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_0/bd_1ba7_microblaze_I_0_ooc_debug.xdc
+add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_0/bd_1ba7_microblaze_I_0.xdc
+add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_9/bd_1ba7_second_lmb_bram_I_0_ooc.xdc
+add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_6/bd_1ba7_lmb_bram_I_0_ooc.xdc
+add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_3/bd_1ba7_dlmb_0.xdc
+add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/bd_1ba7_ooc.xdc
+add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_board.xdc
+add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_ooc.xdc
+add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/xlnx_ddr4_board.xdc
+add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/par/xlnx_ddr4.xdc
+add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_ooc.xdc
+add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_clocks.xdc
+add_files -fileset constrs_1 -norecurse IP/xlnx_ahblite_axi_bridge.runs/xlnx_ahblite_axi_bridge_synth_1/dont_touch.xdc
+add_files -fileset constrs_1 -norecurse IP/xlnx_ahblite_axi_bridge.gen/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge_ooc.xdc
+add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.runs/xlnx_proc_sys_reset_synth_1/dont_touch.xdc
+add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_ooc.xdc
+add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xdc
+add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_board.xdc
+#add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.runs/xlnx_axi_clock_converter_synth_1/.Xil/xlnx_axi_clock_converter_propImpl.xdc
+add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.runs/xlnx_axi_clock_converter_synth_1/dont_touch.xdc
+#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.runs/xlnx_ddr4_synth_1/.Xil/xlnx_ddr4_propImpl.xdc
+add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.runs/xlnx_ddr4_synth_1/dont_touch.xdc
+
+# constraints for wally top level
+add_files -fileset constrs_1 -norecurse ../constraints/constraints.xdc
+
+# define top level
+set_property top fpgaTop [current_fileset]
+
+update_compile_order -fileset sources_1
+
+# this is elaboration not synthesis.
+synth_design -rtl -name rtl_1
+
+# this does synthesis? wtf?
+launch_runs synth_1 -jobs 4
+
+wait_on_run synth_1
+open_run synth_1
+
+exec mkdir -p reports/
+exec rm -rf reports/*
+
+check_timing -verbose                                                   -file reports/check_timing.rpt
+report_timing -max_paths 10 -nworst 10 -delay_type max -sort_by slack   -file reports/timing_WORST_10.rpt
+report_timing -nworst 1 -delay_type max -sort_by group                  -file reports/timing.rpt
+report_utilization -hierarchical                                        -file reports/utilization.rpt
+report_cdc                                                              -file reports/cdc.rpt
+report_clock_interaction                                                -file reports/clock_interaction.rpt
diff --git a/fpga/generator/xlnx_axi_clock_converter.tcl b/fpga/generator/xlnx_axi_clock_converter.tcl
index ed038bf4..c63d8761 100644
--- a/fpga/generator/xlnx_axi_clock_converter.tcl
+++ b/fpga/generator/xlnx_axi_clock_converter.tcl
@@ -11,7 +11,7 @@ set_property board_part $boardName [current_project]
 
 create_ip -name axi_clock_converter -vendor xilinx.com -library ip -module_name $ipName
 
-set_property -dict [list CONFIG.ACLK_ASYNC {1} CONFIG.PROTOCOL {AXI4} CONFIG.ADDR_WIDTH {31} CONFIG.DATA_WIDTH {64} CONFIG.ID_WIDTH {4}] [get_ips $ipName]
+set_property -dict [list CONFIG.ACLK_ASYNC {1} CONFIG.PROTOCOL {AXI4} CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {64} CONFIG.ID_WIDTH {4}] [get_ips $ipName]
 
 generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
 generate_target all [get_files  ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v
index e902627c..eb78e89d 100644
--- a/fpga/src/fpgaTop.v
+++ b/fpga/src/fpgaTop.v
@@ -69,7 +69,8 @@ module fpgaTop
   wire 		peripheral_reset;
   wire 		interconnect_aresetn;
   wire 		peripheral_aresetn;
-
+  wire 		mb_reset;
+  
   wire [`AHBW-1:0] HRDATAEXT;
   wire 		   HREADYEXT;
   wire 		   HRESPEXT;
@@ -130,12 +131,17 @@ module fpgaTop
   wire 		   m_axi_rlast;
   wire 		   m_axi_rready;
 
+  wire [3:0] 	   BUS_axi_arregion;
+  wire [3:0] 	   BUS_axi_arqos;
+  wire [3:0] 	   BUS_axi_awregion;
+  wire [3:0] 	   BUS_axi_awqos;
+
   wire [3:0] 	   BUS_axi_awid;
   wire [7:0] 	   BUS_axi_awlen;
   wire [2:0] 	   BUS_axi_awsize;
   wire [1:0] 	   BUS_axi_awburst;
   wire [3:0] 	   BUS_axi_awcache;
-  wire [31:0] 	   BUS_axi_awaddr;
+  wire [30:0] 	   BUS_axi_awaddr;
   wire [2:0] 	   BUS_axi_awprot;
   wire 		   BUS_axi_awvalid;
   wire 		   BUS_axi_awready;
@@ -156,7 +162,7 @@ module fpgaTop
   wire [2:0] 	   BUS_axi_arprot;
   wire [3:0] 	   BUS_axi_arcache;
   wire 		   BUS_axi_arvalid;
-  wire [31:0] 	   BUS_axi_araddr;
+  wire [30:0] 	   BUS_axi_araddr;
   wire 		   BUS_axi_arlock;
   wire 		   BUS_axi_arready;
   wire [3:0] 	   BUS_axi_rid;
@@ -189,16 +195,16 @@ module fpgaTop
   IOBUF iobufSDCMD(.T(~SDCCmdOE), // iobuf's T is active low
 		   .I(SDCCmdIn),
 		   .O(SDCCmdOut),
-		   .IO(SDCmd));
+		   .IO(SDCCmd));
 
   // reset controller XILINX IP
-  wrapper_proc_sys_reset_0_0 wrapper_proc_sys_reset_0_0
+  xlnx_proc_sys_reset xlnx_proc_sys_reset_0
     (.slowest_sync_clk(CPUCLK),
      .ext_reset_in(c0_ddr4_ui_clk_sync_rst),
      .aux_reset_in(south_rst),
      .mb_debug_sys_rst(1'b0),
      .dcm_locked(c0_init_calib_complete),
-     //.mb_reset,  //open
+     .mb_reset(mb_reset),  //open
      .bus_struct_reset(bus_struct_reset),
      .peripheral_reset(peripheral_reset), //open
      .interconnect_aresetn(interconnect_aresetn), //open
@@ -208,7 +214,7 @@ module fpgaTop
   // wally
   wallypipelinedsoc wallypipelinedsoc
     (.clk(CPUCLK),
-     .reset(bus_struct_reset),
+     .reset_ext(bus_struct_reset),
      // bus interface
      .HRDATAEXT(HRDATAEXT),
      .HREADYEXT(HREADYEXT),
@@ -237,13 +243,12 @@ module fpgaTop
      .SDCCmdIn(SDCCmdIn),     
      .SDCCmdOut(SDCCmdOut),
      .SDCCmdOE(SDCCmdOE),
-     
-     );
+     .SDCCLK(SDCCLK));
 
   // ahb lite to axi bridge
   xlnx_ahblite_axi_bridge xlnx_ahblite_axi_bridge_0
     (.s_ahb_hclk(CPUCLK),
-     .s_ahb_hresetn(peripheral_aresetn)
+     .s_ahb_hresetn(peripheral_aresetn),
      .s_ahb_hsel(HSELEXT),
      .s_ahb_haddr(HADDR),
      .s_ahb_hprot(HPROT),
@@ -300,8 +305,10 @@ module fpgaTop
      .s_axi_awsize(m_axi_awsize),
      .s_axi_awburst(m_axi_awburst),
      .s_axi_awcache(m_axi_awcache),
-     .s_axi_awaddr(m_axi_awaddr),
+     .s_axi_awaddr(m_axi_awaddr[30:0]),
      .s_axi_awprot(m_axi_awprot),
+     .s_axi_awregion(4'b0), // this could be a bug. bridge does not have these outputs
+     .s_axi_awqos(4'b0),    // this could be a bug. bridge does not have these outputs
      .s_axi_awvalid(m_axi_awvalid),
      .s_axi_awready(m_axi_awready),
      .s_axi_awlock(m_axi_awlock),
@@ -319,9 +326,11 @@ module fpgaTop
      .s_axi_arsize(m_axi_arsize),
      .s_axi_arburst(m_axi_arburst),
      .s_axi_arprot(m_axi_arprot),
+     .s_axi_arregion(4'b0), // this could be a bug. bridge does not have these outputs
+     .s_axi_arqos(4'b0),    // this could be a bug. bridge does not have these outputs
      .s_axi_arcache(m_axi_arcache),
      .s_axi_arvalid(m_axi_arvalid),
-     .s_axi_araddr(m_axi_araddr),
+     .s_axi_araddr(m_axi_araddr[30:0]),
      .s_axi_arlock(m_axi_arlock),
      .s_axi_arready(m_axi_arready),
      .s_axi_rid(m_axi_rid),
@@ -340,6 +349,8 @@ module fpgaTop
      .m_axi_awcache(BUS_axi_awcache),
      .m_axi_awaddr(BUS_axi_awaddr),
      .m_axi_awprot(BUS_axi_awprot),
+     .m_axi_awregion(BUS_axi_awregion),
+     .m_axi_awqos(BUS_axi_awqos),
      .m_axi_awvalid(BUS_axi_awvalid),
      .m_axi_awready(BUS_axi_awready),
      .m_axi_awlock(BUS_axi_awlock),
@@ -357,6 +368,8 @@ module fpgaTop
      .m_axi_arsize(BUS_axi_arsize),
      .m_axi_arburst(BUS_axi_arburst),
      .m_axi_arprot(BUS_axi_arprot),
+     .m_axi_arregion(BUS_axi_arregion),
+     .m_axi_arqos(BUS_axi_arqos),
      .m_axi_arcache(BUS_axi_arcache),
      .m_axi_arvalid(BUS_axi_arvalid),
      .m_axi_araddr(BUS_axi_araddr),
@@ -398,7 +411,7 @@ module fpgaTop
 
      // axi
      .c0_ddr4_s_axi_awid(BUS_axi_awid),
-     .c0_ddr4_s_axi_awaddr(BUS_axi_awaddr),
+     .c0_ddr4_s_axi_awaddr(BUS_axi_awaddr[30:0]),
      .c0_ddr4_s_axi_awlen(BUS_axi_awlen),
      .c0_ddr4_s_axi_awsize(BUS_axi_awsize),
      .c0_ddr4_s_axi_awburst(BUS_axi_awburst),
@@ -418,7 +431,7 @@ module fpgaTop
      .c0_ddr4_s_axi_bresp(BUS_axi_bresp),
      .c0_ddr4_s_axi_bvalid(BUS_axi_bvalid),
      .c0_ddr4_s_axi_arid(BUS_axi_arid),
-     .c0_ddr4_s_axi_araddr(BUS_axi_araddr),
+     .c0_ddr4_s_axi_araddr(BUS_axi_araddr[30:0]),
      .c0_ddr4_s_axi_arlen(BUS_axi_arlen),
      .c0_ddr4_s_axi_arsize(BUS_axi_arsize),
      .c0_ddr4_s_axi_arburst(BUS_axi_arburst),