From e709ad4145a970df71d8a27c0c912d13ee09bd0c Mon Sep 17 00:00:00 2001
From: cturek <cturek@hmc.edu>
Date: Sat, 3 Sep 2022 22:09:55 +0000
Subject: [PATCH] Old changes to old files

---
 pipelined/srt/srt.sv       | 4 ++--
 pipelined/srt/testbench.sv | 8 ++++----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/pipelined/srt/srt.sv b/pipelined/srt/srt.sv
index 3f6cad5f..72dd46c8 100644
--- a/pipelined/srt/srt.sv
+++ b/pipelined/srt/srt.sv
@@ -163,7 +163,7 @@ module srtpreproc (
   assign D = {4'b0001, Int ? PreprocB : PreprocY};
 
   // Integer exponent and sign calculations
-  assign intExp = zeroCntB - zeroCntA - Mod + (PreprocA >= PreprocB);
+  assign intExp = zeroCntB - zeroCntA + (PreprocA >= PreprocB);
   assign intSign = Signed & (SrcA[`XLEN - 1] ^ SrcB[`XLEN - 1]);
 
   // Number of cycles of divider
@@ -462,7 +462,7 @@ module srtpostproc(
   end
   assign floatRes = S[`DIVLEN] ? S[`DIVLEN:1] : S[`DIVLEN-1:0];
   assign intRes = intS[`DIVLEN] ? intS[`DIVLEN:1] : intS[`DIVLEN-1:0];
-  assign shiftRem = (intRem >> (zeroCntD));
+  assign shiftRem = (intRem >> (zeroCntD+1));
   always_comb begin
     if (Int) begin
       if (Mod) Result = shiftRem[`DIVLEN-1:0];
diff --git a/pipelined/srt/testbench.sv b/pipelined/srt/testbench.sv
index 1b40c673..6d061c62 100644
--- a/pipelined/srt/testbench.sv
+++ b/pipelined/srt/testbench.sv
@@ -70,9 +70,9 @@ module testbench;
   integer testnum, errors;
 
   // Equip Int, Sqrt, or IntMod test
-  assign Int =  1'b0;
-  assign Mod =  1'b0;
-  assign Sqrt = 1'b1;
+  assign Int =  1'b1;
+  assign Mod =  1'b1;
+  assign Sqrt = 1'b0;
 
   // Divider
   srt srt(.clk, .Start(req), 
@@ -101,7 +101,7 @@ module testbench;
     begin
       testnum = 0; 
       errors = 0;
-      $readmemh ("sqrttestvectors", Tests);
+      $readmemh ("modtestvectors", Tests);
       Vec = Tests[testnum];
       a = Vec[`mema];
       {asign, aExp, afrac} = a;