From 3c49fd08f6a2dd3307d090693396af194dbfc0f0 Mon Sep 17 00:00:00 2001 From: Thomas Fleming Date: Wed, 14 Apr 2021 20:20:34 -0400 Subject: [PATCH 1/2] Remove imem from testbenches --- wally-pipelined/src/wally/wallypipelinedsoc.sv | 5 ++++- wally-pipelined/testbench/testbench-busybear.sv | 2 -- wally-pipelined/testbench/testbench-coremark.sv | 1 - wally-pipelined/testbench/testbench-coremark_bare.sv | 1 - wally-pipelined/testbench/testbench-imperas.sv | 2 -- wally-pipelined/testbench/testbench-privileged.sv | 2 -- 6 files changed, 4 insertions(+), 9 deletions(-) diff --git a/wally-pipelined/src/wally/wallypipelinedsoc.sv b/wally-pipelined/src/wally/wallypipelinedsoc.sv index c91c3494..9111b59a 100644 --- a/wally-pipelined/src/wally/wallypipelinedsoc.sv +++ b/wally-pipelined/src/wally/wallypipelinedsoc.sv @@ -72,6 +72,9 @@ module wallypipelinedsoc ( // instantiate processor and memories wallypipelinedhart hart(.*); - imem imem(.AdrF(PCF[`XLEN-1:1]), .*); // temporary until uncore memory is finished*** + // *** Temporary driving of access fault to low until PMA checker is complete + assign InstrAccessFaultF = '0; + // instructions now come from uncore memory. This line can be removed at any time. + // imem imem(.AdrF(PCF[`XLEN-1:1]), .*); // temporary until uncore memory is finished*** uncore uncore(.HWDATAIN(HWDATA), .*); endmodule \ No newline at end of file diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv index 4490990e..a7da0352 100644 --- a/wally-pipelined/testbench/testbench-busybear.sv +++ b/wally-pipelined/testbench/testbench-busybear.sv @@ -99,8 +99,6 @@ module testbench_busybear(); initial begin $readmemh("/courses/e190ax/busybear_boot_new/bootmem.txt", dut.uncore.bootdtim.RAM, 'h1000 >> 3); $readmemh("/courses/e190ax/busybear_boot_new/ram.txt", dut.uncore.dtim.RAM); - $readmemh("/courses/e190ax/busybear_boot_new/bootmem.txt", dut.imem.bootram, 'h1000 >> 3); - $readmemh("/courses/e190ax/busybear_boot_new/ram.txt", dut.imem.RAM); $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.Predictor.DirPredictor.PHT.memory); $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.TargetPredictor.memory.memory); end diff --git a/wally-pipelined/testbench/testbench-coremark.sv b/wally-pipelined/testbench/testbench-coremark.sv index eae3ebdc..3c4f5e57 100644 --- a/wally-pipelined/testbench/testbench-coremark.sv +++ b/wally-pipelined/testbench/testbench-coremark.sv @@ -78,7 +78,6 @@ module testbench(); totalerrors = 0; // read test vectors into memory memfilename = tests[0]; - $readmemh(memfilename, dut.imem.RAM); $readmemh(memfilename, dut.uncore.dtim.RAM); for(j=18710; j < 65535; j = j+1) dut.uncore.dtim.RAM[j] = 64'b0; diff --git a/wally-pipelined/testbench/testbench-coremark_bare.sv b/wally-pipelined/testbench/testbench-coremark_bare.sv index 12785539..3f2af76b 100644 --- a/wally-pipelined/testbench/testbench-coremark_bare.sv +++ b/wally-pipelined/testbench/testbench-coremark_bare.sv @@ -80,7 +80,6 @@ module testbench(); totalerrors = 0; // read test vectors into memory memfilename = tests[0]; - $readmemh(memfilename, dut.imem.RAM); $readmemh(memfilename, dut.uncore.dtim.RAM); for(j=268437702; j < 268566528; j = j+1) dut.uncore.dtim.RAM[j] = 64'b0; diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 4f6be782..1e0bd95a 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -450,7 +450,6 @@ module testbench(); end // read test vectors into memory memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"}; - $readmemh(memfilename, dut.imem.RAM); $readmemh(memfilename, dut.uncore.dtim.RAM); ProgramAddrMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.addr"}; ProgramLabelMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.lab"}; @@ -525,7 +524,6 @@ module testbench(); end else begin memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"}; - $readmemh(memfilename, dut.imem.RAM); $readmemh(memfilename, dut.uncore.dtim.RAM); $display("Read memfile %s", memfilename); ProgramAddrMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.addr"}; diff --git a/wally-pipelined/testbench/testbench-privileged.sv b/wally-pipelined/testbench/testbench-privileged.sv index 4e7227c6..a10959b3 100644 --- a/wally-pipelined/testbench/testbench-privileged.sv +++ b/wally-pipelined/testbench/testbench-privileged.sv @@ -116,7 +116,6 @@ module testbench(); end // read test vectors into memory memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"}; - $readmemh(memfilename, dut.imem.RAM); $readmemh(memfilename, dut.uncore.dtim.RAM); ProgramAddrMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.addr"}; ProgramLabelMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.lab"}; @@ -191,7 +190,6 @@ module testbench(); end else begin memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"}; - $readmemh(memfilename, dut.imem.RAM); $readmemh(memfilename, dut.uncore.dtim.RAM); $display("Read memfile %s", memfilename); ProgramAddrMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.addr"};