diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh index ccad97cb..4ef61acf 100644 --- a/pipelined/config/buildroot/wally-config.vh +++ b/pipelined/config/buildroot/wally-config.vh @@ -44,7 +44,7 @@ `define COUNTERS 32 // LSU microarchitectural Features -`define BUS 1 +`define BUS_SUPPORTED 1 `define DCACHE 1 `define ICACHE 1 `define VIRTMEM_SUPPORTED 1 diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh index ddbb18c0..ca5261cf 100644 --- a/pipelined/config/fpga/wally-config.vh +++ b/pipelined/config/fpga/wally-config.vh @@ -45,7 +45,7 @@ `define COUNTERS 32 // LSU microarchitectural Features -`define BUS 1 +`define BUS_SUPPORTED 1 `define DCACHE 1 `define ICACHE 1 `define VIRTMEM_SUPPORTED 1 diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh index c81faeb8..8a1bc54e 100644 --- a/pipelined/config/rv32e/wally-config.vh +++ b/pipelined/config/rv32e/wally-config.vh @@ -46,7 +46,7 @@ `define ZFH_SUPPORTED 0 // LSU microarchitectural Features -`define BUS 1 +`define BUS_SUPPORTED 1 `define DCACHE 0 `define ICACHE 0 `define VIRTMEM_SUPPORTED 0 diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh index 94d56d83..e18c99b6 100644 --- a/pipelined/config/rv32gc/wally-config.vh +++ b/pipelined/config/rv32gc/wally-config.vh @@ -45,7 +45,7 @@ `define ZFH_SUPPORTED 0 // LSU microarchitectural Features -`define BUS 1 +`define BUS_SUPPORTED 1 `define DCACHE 1 `define ICACHE 1 `define VIRTMEM_SUPPORTED 1 diff --git a/pipelined/config/rv32i/wally-config.vh b/pipelined/config/rv32i/wally-config.vh index 80a4773d..23fa30fa 100644 --- a/pipelined/config/rv32i/wally-config.vh +++ b/pipelined/config/rv32i/wally-config.vh @@ -46,7 +46,7 @@ `define ZFH_SUPPORTED 0 // LSU microarchitectural Features -`define BUS 0 +`define BUS_SUPPORTED 0 `define DCACHE 0 `define ICACHE 0 `define VIRTMEM_SUPPORTED 0 diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh index eb662762..7f210ee8 100644 --- a/pipelined/config/rv32ic/wally-config.vh +++ b/pipelined/config/rv32ic/wally-config.vh @@ -45,7 +45,7 @@ `define ZFH_SUPPORTED 0 // LSU microarchitectural Features -`define BUS 1 +`define BUS_SUPPORTED 1 `define DCACHE 0 `define ICACHE 0 `define VIRTMEM_SUPPORTED 0 diff --git a/pipelined/config/rv64fpquad/wally-config.vh b/pipelined/config/rv64fpquad/wally-config.vh index 2570ff1d..6072ea45 100644 --- a/pipelined/config/rv64fpquad/wally-config.vh +++ b/pipelined/config/rv64fpquad/wally-config.vh @@ -46,7 +46,7 @@ `define ZFH_SUPPORTED 1 // LSU microarchitectural Features -`define BUS 1 +`define BUS_SUPPORTED 1 `define DCACHE 1 `define ICACHE 1 `define VIRTMEM_SUPPORTED 1 diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index bdef122f..c24f4538 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -46,7 +46,7 @@ `define ZFH_SUPPORTED 0 // LSU microarchitectural Features -`define BUS 1 +`define BUS_SUPPORTED 1 `define DCACHE 1 `define ICACHE 1 `define VIRTMEM_SUPPORTED 1 diff --git a/pipelined/config/rv64i/wally-config.vh b/pipelined/config/rv64i/wally-config.vh index bb7b71c0..2f01f50c 100644 --- a/pipelined/config/rv64i/wally-config.vh +++ b/pipelined/config/rv64i/wally-config.vh @@ -46,7 +46,7 @@ `define ZFH_SUPPORTED 0 // LSU microarchitectural Features -`define BUS 0 +`define BUS_SUPPORTED 0 `define DCACHE 0 `define ICACHE 0 `define VIRTMEM_SUPPORTED 0 diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 0010403a..ee074587 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -208,7 +208,7 @@ module ifu ( end else begin assign IFURWF = 2'b10; end - if (`BUS) begin : bus + if (`BUS_SUPPORTED) begin : bus // **** must fix words per line vs beats per line as in lsu. localparam WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1; localparam LOGBWPL = `ICACHE ? $clog2(WORDSPERLINE) : 1; diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 19f5ba96..c28dc500 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -206,7 +206,7 @@ module lsu ( assign {LoadPageFaultM, StoreAmoPageFaultM} = '0; assign PAdrM = IHAdrM[`PA_BITS-1:0]; assign CacheableM = 1'b1; - assign SelDTIM = `DTIM_SUPPORTED & ~`BUS; // if no PMA then select dtim if there is a DTIM. If there is + assign SelDTIM = `DTIM_SUPPORTED & ~`BUS_SUPPORTED; // if no PMA then select dtim if there is a DTIM. If there is // a bus then this is always 0. Cannot have both without PMA. end @@ -236,7 +236,7 @@ module lsu ( .ReadDataWordM(DTIMReadDataWordM[`XLEN-1:0]), .ByteMaskM(ByteMaskM[`XLEN/8-1:0])); end else begin end - if (`BUS) begin : bus + if (`BUS_SUPPORTED) begin : bus if(`DCACHE) begin : dcache localparam LLENWORDSPERLINE = `DCACHE_LINELENINBITS/`LLEN; // Number of LLEN words in cacheline localparam LLENLOGBWPL = $clog2(LLENWORDSPERLINE); // Log2 of ^ diff --git a/pipelined/src/wally/cvw.sv b/pipelined/src/wally/cvw.sv index 66512e94..5aa6d232 100644 --- a/pipelined/src/wally/cvw.sv +++ b/pipelined/src/wally/cvw.sv @@ -43,7 +43,7 @@ package cvw; parameter COUNTERS = `COUNTERS; parameter ZICOUNTERS_SUPPORTED = `ZICOUNTERS_SUPPORTED; parameter ZFH_SUPPORTED = `ZFH_SUPPORTED; - parameter BUS = `BUS; + parameter BUS_SUPPORTED = `BUS_SUPPORTED; parameter DCACHE = `DCACHE; parameter ICACHE = `ICACHE; parameter VIRTMEM_SUPPORTED = `VIRTMEM_SUPPORTED; diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index 5c2c6efc..b5074647 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -237,7 +237,7 @@ module wallypipelinedcore ( .PCF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW, .LSUStallM); - if(BUS) begin : ebu + if(BUS_SUPPORTED) begin : ebu ebu ebu(// IFU connections .clk, .reset, // IFU interface diff --git a/pipelined/src/wally/wallypipelinedsoc.sv b/pipelined/src/wally/wallypipelinedsoc.sv index 26979545..e792f6f8 100644 --- a/pipelined/src/wally/wallypipelinedsoc.sv +++ b/pipelined/src/wally/wallypipelinedsoc.sv @@ -80,7 +80,7 @@ module wallypipelinedsoc ( ); // instantiate uncore if a bus interface exists - if (BUS) begin : uncore + if (BUS_SUPPORTED) begin : uncore uncore uncore(.HCLK, .HRESETn, .TIMECLK, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 2bbe1d11..6d0eec95 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -246,7 +246,7 @@ logic [3:0] dummy; force dut.uncore.uncore.sdc.SDC.LimitTimers = 1; end else begin if (`IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM); - else if (`BUS) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); + else if (`BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); if (`DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM); end @@ -545,7 +545,7 @@ module riscvassertions; assert (`VIRTMEM_SUPPORTED == 0 | (`DTIM_SUPPORTED == 0 & `IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses"); assert (`DCACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache"); assert (`ICACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache"); - assert ((`DCACHE == 0 & `ICACHE == 0) | `BUS) else $error("Dcache and Icache requires DBUS."); + assert ((`DCACHE == 0 & `ICACHE == 0) | `BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS_SUPPORTED."); assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1"); assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words"); assert (`DCACHE | `A_SUPPORTED == 0) else $error("Atomic extension (A) requires cache on Wally."); diff --git a/pipelined/testbench/testbench_imperas.sv b/pipelined/testbench/testbench_imperas.sv index 7e472a99..1bd5d45c 100644 --- a/pipelined/testbench/testbench_imperas.sv +++ b/pipelined/testbench/testbench_imperas.sv @@ -100,8 +100,8 @@ module testbench; pathname = "../../tests/riscof/work/wally-riscv-arch-test/"; memfilename = {pathname, testName, "/ref/ref.elf.memfile"}; - if (`BUS) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); - else $error("Imperas test bench requires BUS."); + if (`BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); + else $error("Imperas test bench requires BUS_SUPPORTED."); ProgramAddrMapFile = {pathname, testName, "/ref/ref.elf.objdump.addr"}; ProgramLabelMapFile = {pathname, testName, "/ref/ref.elf.objdump.lab"}; @@ -287,7 +287,7 @@ module riscvassertions; assert (`VIRTMEM_SUPPORTED == 0 | (`DTIM_SUPPORTED == 0 & `IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses"); assert (`DCACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache"); assert (`ICACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache"); - assert ((`DCACHE == 0 & `ICACHE == 0) | `BUS) else $error("Dcache and Icache requires DBUS."); + assert ((`DCACHE == 0 & `ICACHE == 0) | `BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS."); assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1"); assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words"); assert (`DCACHE | `A_SUPPORTED == 0) else $error("Atomic extension (A) requires cache on Wally.");