From de3a0c644b5b461f4b46a2d6faedc3f77f6aa09e Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 17 Jun 2021 22:27:39 -0400 Subject: [PATCH 1/8] Further cleaning of PMA checker --- wally-pipelined/src/mmu/pmaadrdec.sv | 10 ++++-- wally-pipelined/src/mmu/pmachecker.sv | 51 ++++++++------------------- 2 files changed, 21 insertions(+), 40 deletions(-) diff --git a/wally-pipelined/src/mmu/pmaadrdec.sv b/wally-pipelined/src/mmu/pmaadrdec.sv index a133503b..c48cdc66 100644 --- a/wally-pipelined/src/mmu/pmaadrdec.sv +++ b/wally-pipelined/src/mmu/pmaadrdec.sv @@ -35,14 +35,18 @@ module pmaadrdec ( output logic HSEL ); - logic match; + logic Match; + logic SizeValid; // determine if an address is in a range starting at the base // for example, if Base = 0x04002000 and range = 0x00000FFF, // then anything address between 0x04002000 and 0x04002FFF should match (HSEL=1) + assign Match = &((HADDR ~^ Base) | Range); - assign match = &((HADDR ~^ Base) | Range); - assign HSEL = match & Supported; + // determine if legal size of access is being made (byte, halfword, word, doubleword) + assign SizeValid = SizeMask[Size[1:0]]; + + assign HSEL = Match && Supported && AccessValid && SizeValid; endmodule diff --git a/wally-pipelined/src/mmu/pmachecker.sv b/wally-pipelined/src/mmu/pmachecker.sv index 8821c0cf..b8ecc366 100644 --- a/wally-pipelined/src/mmu/pmachecker.sv +++ b/wally-pipelined/src/mmu/pmachecker.sv @@ -46,14 +46,7 @@ module pmachecker ( output logic PMAStoreAccessFaultM ); - // Signals are high if the memory access is within the given region - logic BootTim, Tim, CLINT, GPIO, UART, PLIC; - logic [5:0] Regions; - - // Actual HSEL signals sent to uncore - logic HSELBootTim, HSELTim, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC; - logic ValidBootTim, ValidTim, ValidCLINT, ValidGPIO, ValidUART, ValidPLIC; - + // logic BootTim, Tim, CLINT, GPIO, UART, PLIC; logic PMAAccessFault; logic AccessRW, AccessRWX, AccessRX; @@ -62,43 +55,27 @@ module pmachecker ( assign AccessRWX = ReadAccessM | WriteAccessM | ExecuteAccessF; assign AccessRX = ReadAccessM | ExecuteAccessF; - // Determine which region of physical memory (if any) is being accessed - pmaadrdec boottimdec(HADDR, `BOOTTIMBASE, `BOOTTIMRANGE, `BOOTTIMSUPPORTED, AccessRX, HSIZE, 4'b1111, BootTim); - pmaadrdec timdec(HADDR, `TIMBASE, `TIMRANGE, `TIMSUPPORTED, AccessRWX, HSIZE, 4'b1111, Tim); - pmaadrdec clintdec(HADDR, `CLINTBASE, `CLINTRANGE, `CLINTSUPPORTED, AccessRW, HSIZE, (`XLEN==64 ? 4'b1000 : 4'b0100), CLINT); - pmaadrdec gpiodec(HADDR, `GPIOBASE, `GPIORANGE, `GPIOSUPPORTED, AccessRW, HSIZE, 4'b0100, GPIO); - pmaadrdec uartdec(HADDR, `UARTBASE, `UARTRANGE, `UARTSUPPORTED, AccessRW, HSIZE, 4'b0001, UART); - pmaadrdec plicdec(HADDR, `PLICBASE, `PLICRANGE, `PLICSUPPORTED, AccessRW, HSIZE, 4'b0100, PLIC); - - // Swizzle region bits - assign Regions = {BootTim, Tim, CLINT, GPIO, UART, PLIC}; + // *** linux tests fail early when Access is anything other than 1b1 + pmaadrdec boottimdec(HADDR, `BOOTTIMBASE, `BOOTTIMRANGE, `BOOTTIMSUPPORTED, 1'b1/*AccessRX*/, HSIZE, 4'b1111, HSELRegions[5]); + pmaadrdec timdec(HADDR, `TIMBASE, `TIMRANGE, `TIMSUPPORTED, 1'b1/*AccessRWX*/, HSIZE, 4'b1111, HSELRegions[4]); + pmaadrdec clintdec(HADDR, `CLINTBASE, `CLINTRANGE, `CLINTSUPPORTED, AccessRW, HSIZE, (`XLEN==64 ? 4'b1000 : 4'b0100), HSELRegions[3]); + pmaadrdec gpiodec(HADDR, `GPIOBASE, `GPIORANGE, `GPIOSUPPORTED, AccessRW, HSIZE, 4'b0100, HSELRegions[2]); + pmaadrdec uartdec(HADDR, `UARTBASE, `UARTRANGE, `UARTSUPPORTED, AccessRW, HSIZE, 4'b0001, HSELRegions[1]); + pmaadrdec plicdec(HADDR, `PLICBASE, `PLICRANGE, `PLICSUPPORTED, AccessRW, HSIZE, 4'b0100, HSELRegions[0]); // Only RAM memory regions are cacheable - assign Cacheable = BootTim | Tim; - assign Idempotent = Tim; - assign AtomicAllowed = Tim; + assign Cacheable = HSELRegions[5] | HSELRegions[4]; + assign Idempotent = HSELRegions[4]; + assign AtomicAllowed = HSELRegions[4]; - assign ValidBootTim = '1; - assign ValidTim = '1; - assign ValidCLINT = ~ExecuteAccessF && ((HSIZE == 3'b011 && `XLEN==64) || (HSIZE == 3'b010 && `XLEN==32)); - assign ValidGPIO = ~ExecuteAccessF && (HSIZE == 3'b010); - assign ValidUART = ~ExecuteAccessF && (HSIZE == 3'b000); - assign ValidPLIC = ~ExecuteAccessF && (HSIZE == 3'b010); - - assign HSELBootTim = BootTim && ValidBootTim; - assign HSELTim = Tim && ValidTim; - assign HSELCLINT = CLINT && ValidCLINT; - assign HSELGPIO = GPIO && ValidGPIO; - assign HSELUART = UART && ValidUART; // only byte writes to UART are supported - assign HSELPLIC = PLIC && ValidPLIC; + /*ExecuteAccessF | ReadAccessM | WriteAccessM; */ // Swizzle region bits - assign HSELRegions = {HSELBootTim, HSELTim, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC}; - - assign PMAAccessFault = ~|HSELRegions; + //assign HSELRegions = {BootTim, Tim, CLINT, GPIO, UART, PLIC}; // Detect access faults + assign PMAAccessFault = ~|HSELRegions; assign PMAInstrAccessFaultF = ExecuteAccessF && PMAAccessFault; assign PMALoadAccessFaultM = ReadAccessM && PMAAccessFault; assign PMAStoreAccessFaultM = WriteAccessM && PMAAccessFault; From 336936cc390ca366b95f4652b0d4cd9a9a96f1bf Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 18 Jun 2021 07:53:49 -0400 Subject: [PATCH 2/8] Cleaned up name of MTIME register in CSRC --- .../regression/vsim_stacktrace.vstf | 1534 +++++++++++++++++ wally-pipelined/regression/wally-busybear.do | 2 +- wally-pipelined/src/privileged/csr.sv | 2 +- wally-pipelined/src/privileged/csrc.sv | 28 +- wally-pipelined/src/privileged/privileged.sv | 2 +- wally-pipelined/src/uncore/uncore.sv | 15 +- .../src/wally/wallypipelinedhart.sv | 2 +- .../src/wally/wallypipelinedsoc.sv | 2 +- .../testbench/testbench-busybear.sv | 5 + wally-pipelined/testbench/testbench-linux.sv | 10 + 10 files changed, 1570 insertions(+), 32 deletions(-) create mode 100644 wally-pipelined/regression/vsim_stacktrace.vstf diff --git a/wally-pipelined/regression/vsim_stacktrace.vstf b/wally-pipelined/regression/vsim_stacktrace.vstf new file mode 100644 index 00000000..e524b917 --- /dev/null +++ b/wally-pipelined/regression/vsim_stacktrace.vstf @@ -0,0 +1,1534 @@ +# Current time Thu Jun 17 21:48:46 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d8b44: '' +# 4 0x00000000010d8bac: '' +# 5 0x00000000010cef65: '' +# 6 0x00000000010d12f0: '' +# 7 0x00000000010d4700: '' +# 8 0x00000000007cded8: '' +# 9 0x0000000000809da8: '' +# 10 0x000000000081d399: '' +# 11 0x00000000007cb83e: '' +# 12 0x00007feff06c6549: '../testbench/testbench-linux.sv:536' +# 13 0x000000000276f58a: '' +# 14 0x0000000000554abb: '' +# 15 0x00000000006e7153: '' +# 16 0x0000000000c01b55: '' +# 17 0x0000000000c069ab: '' +# 18 0x0000000000c0828e: '' +# 19 0x0000000000ebfecd: '' +# 20 0x0000000002bdcfdd: '' +# 21 0x0000000002be1436: '' +# 22 0x0000000002be2b21: '' +# 23 0x0000000002be2e86: '' +# 24 0x0000000001125d89: '' +# 25 0x0000000002c82d8f: '' +# 26 0x0000000002cd6907: '' +# 27 0x0000000002c997f7: '' +# 28 0x0000000002c99ad9: '' +# 29 0x0000000002a9bfdd: '' +# 30 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Thu Jun 17 21:48:46 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Thu Jun 17 21:50:07 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d8b44: '' +# 4 0x00000000010d8bac: '' +# 5 0x00000000010cef65: '' +# 6 0x00000000010d12f0: '' +# 7 0x00000000010d4700: '' +# 8 0x00000000007cded8: '' +# 9 0x0000000000809da8: '' +# 10 0x000000000081d399: '' +# 11 0x00000000007cb83e: '' +# 12 0x00007feff06c6549: '../testbench/testbench-linux.sv:536' +# 13 0x000000000276f58a: '' +# 14 0x0000000000554abb: '' +# 15 0x00000000006e7153: '' +# 16 0x0000000000c01b55: '' +# 17 0x0000000000c069ab: '' +# 18 0x0000000000c0828e: '' +# 19 0x0000000000ebfecd: '' +# 20 0x0000000002bdcfdd: '' +# 21 0x0000000002be1436: '' +# 22 0x0000000002be2b21: '' +# 23 0x0000000002be2e86: '' +# 24 0x0000000001125d89: '' +# 25 0x0000000002c82d8f: '' +# 26 0x0000000002cd6907: '' +# 27 0x0000000002c997f7: '' +# 28 0x0000000002c99ad9: '' +# 29 0x0000000002a9bfdd: '' +# 30 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Thu Jun 17 21:50:07 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Thu Jun 17 22:04:29 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x00000000027777ef: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d8b44: '' +# 4 0x00000000010d8bac: '' +# 5 0x0000000000f5be1c: '' +# 6 0x0000000000b98fd0: '' +# 7 0x0000000000b9923c: '' +# 8 0x0000000000b9b3f0: '' +# 9 0x000000000057f81c: '' +# 10 0x00000000006e7153: '' +# 11 0x0000000000c01b55: '' +# 12 0x0000000000c069ab: '' +# 13 0x0000000000c0828e: '' +# 14 0x0000000000ebfecd: '' +# 15 0x0000000002bdcfdd: '' +# 16 0x0000000002be1436: '' +# 17 0x0000000002be2b21: '' +# 18 0x0000000002be2e86: '' +# 19 0x0000000001125d89: '' +# 20 0x0000000002c82d8f: '' +# 21 0x0000000002cd6907: '' +# 22 0x0000000002c997f7: '' +# 23 0x0000000002c99ad9: '' +# 24 0x0000000002a9bfdd: '' +# 25 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Thu Jun 17 22:29:27 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d8b44: '' +# 4 0x00000000010d8bac: '' +# 5 0x00000000010cef65: '' +# 6 0x00000000010d12f0: '' +# 7 0x00000000010d4700: '' +# 8 0x00000000007cded8: '' +# 9 0x0000000000809da8: '' +# 10 0x000000000081d399: '' +# 11 0x00000000007cb83e: '' +# 12 0x00007feff06c5cf9: '../testbench/testbench-linux.sv:536' +# 13 0x000000000276f58a: '' +# 14 0x0000000000554abb: '' +# 15 0x00000000006e7153: '' +# 16 0x0000000000c01b55: '' +# 17 0x0000000000c069ab: '' +# 18 0x0000000000c0828e: '' +# 19 0x0000000000ebfecd: '' +# 20 0x0000000002bdcfdd: '' +# 21 0x0000000002be1436: '' +# 22 0x0000000002be2b21: '' +# 23 0x0000000002be2e86: '' +# 24 0x0000000001125d89: '' +# 25 0x0000000002c82d8f: '' +# 26 0x0000000002cd6907: '' +# 27 0x0000000002c997f7: '' +# 28 0x0000000002c99ad9: '' +# 29 0x0000000002a9bfdd: '' +# 30 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Thu Jun 17 22:29:27 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Thu Jun 17 22:32:57 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d872e: '' +# 4 0x00000000010d887b: '' +# 5 0x00000000010d96f4: '' +# 6 0x000000000061ce93: '' +# 7 0x000000000062a516: '' +# 8 0x00007fefec49a00a: '../testbench/testbench-linux.sv:536' +# 9 0x000000000276f58a: '' +# 10 0x0000000000554abb: '' +# 11 0x00000000006e7153: '' +# 12 0x0000000000c01b55: '' +# 13 0x0000000000c069ab: '' +# 14 0x0000000000c0828e: '' +# 15 0x0000000000ebfecd: '' +# 16 0x0000000002bdcfdd: '' +# 17 0x0000000002be1436: '' +# 18 0x0000000002be2b21: '' +# 19 0x0000000002be2e86: '' +# 20 0x0000000001125d89: '' +# 21 0x0000000002c82d8f: '' +# 22 0x0000000002cd6907: '' +# 23 0x0000000002c997f7: '' +# 24 0x0000000002c99ad9: '' +# 25 0x0000000002a9bfdd: '' +# 26 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Thu Jun 17 22:32:57 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Thu Jun 17 22:41:45 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d8b44: '' +# 4 0x00000000010d8bac: '' +# 5 0x00000000010cef65: '' +# 6 0x00000000010d12f0: '' +# 7 0x00000000010d4700: '' +# 8 0x00000000007cded8: '' +# 9 0x0000000000809da8: '' +# 10 0x000000000081d399: '' +# 11 0x00000000007cb83e: '' +# 12 0x00007feff06c5cf9: '../testbench/testbench-linux.sv:536' +# 13 0x000000000276f58a: '' +# 14 0x0000000000554abb: '' +# 15 0x00000000006e7153: '' +# 16 0x0000000000c01b55: '' +# 17 0x0000000000c069ab: '' +# 18 0x0000000000c0828e: '' +# 19 0x0000000000ebfecd: '' +# 20 0x0000000002bdcfdd: '' +# 21 0x0000000002be1436: '' +# 22 0x0000000002be2b21: '' +# 23 0x0000000002be2e86: '' +# 24 0x0000000001125d89: '' +# 25 0x0000000002c82d8f: '' +# 26 0x0000000002cd6907: '' +# 27 0x0000000002c997f7: '' +# 28 0x0000000002c99ad9: '' +# 29 0x0000000002a9bfdd: '' +# 30 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Thu Jun 17 22:41:45 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Thu Jun 17 22:42:25 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d872e: '' +# 4 0x00000000010d887b: '' +# 5 0x00000000010d96f4: '' +# 6 0x000000000061ce93: '' +# 7 0x000000000062a516: '' +# 8 0x00007fefec49a00a: '../testbench/testbench-linux.sv:536' +# 9 0x000000000276f58a: '' +# 10 0x0000000000554abb: '' +# 11 0x00000000006e7153: '' +# 12 0x0000000000c01b55: '' +# 13 0x0000000000c069ab: '' +# 14 0x0000000000c0828e: '' +# 15 0x0000000000ebfecd: '' +# 16 0x0000000002bdcfdd: '' +# 17 0x0000000002be1436: '' +# 18 0x0000000002be2b21: '' +# 19 0x0000000002be2e86: '' +# 20 0x0000000001125d89: '' +# 21 0x0000000002c82d8f: '' +# 22 0x0000000002cd6907: '' +# 23 0x0000000002c997f7: '' +# 24 0x0000000002c99ad9: '' +# 25 0x0000000002a9bfdd: '' +# 26 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Thu Jun 17 22:42:25 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Thu Jun 17 22:49:19 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d8b44: '' +# 4 0x00000000010d8bac: '' +# 5 0x00000000010cef65: '' +# 6 0x00000000010d12f0: '' +# 7 0x00000000010d4700: '' +# 8 0x00000000007cded8: '' +# 9 0x0000000000809da8: '' +# 10 0x000000000081d399: '' +# 11 0x00000000007cb83e: '' +# 12 0x00007feff06c5cf9: '../testbench/testbench-linux.sv:536' +# 13 0x000000000276f58a: '' +# 14 0x0000000000554abb: '' +# 15 0x00000000006e7153: '' +# 16 0x0000000000c01b55: '' +# 17 0x0000000000c069ab: '' +# 18 0x0000000000c0828e: '' +# 19 0x0000000000ebfecd: '' +# 20 0x0000000002bdcfdd: '' +# 21 0x0000000002be1436: '' +# 22 0x0000000002be2b21: '' +# 23 0x0000000002be2e86: '' +# 24 0x0000000001125d89: '' +# 25 0x0000000002c82d8f: '' +# 26 0x0000000002cd6907: '' +# 27 0x0000000002c997f7: '' +# 28 0x0000000002c99ad9: '' +# 29 0x0000000002a9bfdd: '' +# 30 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Thu Jun 17 22:49:19 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 01:12:23 2021 +# Program = vsim +# Id = "2021.2_1" +# Version = "2021.05" +# Date = "May 15 2021" +# Platform = "linux_x86_64" +# Signature = dfcd0de65e8129bcb66fdbdef15ad702 +# 0 0x0000000003466f2d: '' +# 1 0x0000000000fc45c0: '' +# 2 0x00000000010f3e57: '' +# 3 0x00000000010f3f1e: '' +# 4 0x00000000010f406b: '' +# 5 0x00000000010f4ee4: '' +# 6 0x0000000000610603: '' +# 7 0x000000000061e1e6: '' +# 8 0x00007feff0365c5a: '../testbench/testbench-linux.sv:536' +# 9 0x000000000345ecda: '' +# 10 0x00000000004c6e84: '' +# 11 0x00000000006e8203: '' +# 12 0x0000000000c03175: '' +# 13 0x0000000000c08033: '' +# 14 0x0000000000c09d8e: '' +# 15 0x0000000000ed3f8d: '' +# 16 0x00000000038ee98d: '' +# 17 0x00000000038f2de6: '' +# 18 0x00000000038f44d1: '' +# 19 0x00000000038f4836: '' +# 20 0x0000000001145ab9: '' +# 21 0x000000000399473f: '' +# 22 0x00000000039e82b7: '' +# 23 0x00000000039ab1a7: '' +# 24 0x00000000039ab489: '' +# 25 0x0000000003790c2d: '' +# 26 0x0000000000bcf05c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 01:12:23 2021 +# Program = vsim +# Id = "2021.2_1" +# Version = "2021.05" +# Date = "May 15 2021" +# Platform = "linux_x86_64" +# Signature = dfcd0de65e8129bcb66fdbdef15ad702 +# 0 0x0000000003466f2d: '' +# 1 0x00000000034671a6: '' +# 2 0x0000000000753790: '' +# 3 0x000000000347e9d9: '' +# 4 0x0000000000753862: '' +# 5 0x00000000006a853d: '' +# 6 0x0000000000f63259: '' +# 7 0x0000000000c02e65: '' +# 8 0x0000000000c037ba: '' +# 9 0x0000000000c08033: '' +# 10 0x0000000000c09d8e: '' +# 11 0x0000000000ed3f8d: '' +# 12 0x00000000038ee98d: '' +# 13 0x00000000038f2de6: '' +# 14 0x00000000038f44d1: '' +# 15 0x00000000038f4836: '' +# 16 0x0000000001145ab9: '' +# 17 0x000000000399473f: '' +# 18 0x00000000039e82b7: '' +# 19 0x00000000039ab1a7: '' +# 20 0x00000000039ab489: '' +# 21 0x0000000003790c2d: '' +# 22 0x0000000000bcf05c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:14:05 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d8b44: '' +# 4 0x00000000010d8bac: '' +# 5 0x00000000010cef65: '' +# 6 0x00000000010d12f0: '' +# 7 0x00000000010d4700: '' +# 8 0x00000000007cded8: '' +# 9 0x0000000000809da8: '' +# 10 0x000000000081d399: '' +# 11 0x00000000007cb83e: '' +# 12 0x00007feff06c5d19: '../testbench/testbench-linux.sv:536' +# 13 0x000000000276f58a: '' +# 14 0x0000000000554abb: '' +# 15 0x00000000006e7153: '' +# 16 0x0000000000c01b55: '' +# 17 0x0000000000c069ab: '' +# 18 0x0000000000c0828e: '' +# 19 0x0000000000ebfecd: '' +# 20 0x0000000002bdcfdd: '' +# 21 0x0000000002be1436: '' +# 22 0x0000000002be2b21: '' +# 23 0x0000000002be2e86: '' +# 24 0x0000000001125d89: '' +# 25 0x0000000002c82d8f: '' +# 26 0x0000000002cd6907: '' +# 27 0x0000000002c997f7: '' +# 28 0x0000000002c99ad9: '' +# 29 0x0000000002a9bfdd: '' +# 30 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:14:05 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:17:46 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d872e: '' +# 4 0x00000000010d887b: '' +# 5 0x00000000010d96f4: '' +# 6 0x000000000061ce93: '' +# 7 0x000000000062a516: '' +# 8 0x00007fefec49a00a: '../testbench/testbench-linux.sv:536' +# 9 0x000000000276f58a: '' +# 10 0x0000000000554abb: '' +# 11 0x00000000006e7153: '' +# 12 0x0000000000c01b55: '' +# 13 0x0000000000c069ab: '' +# 14 0x0000000000c0828e: '' +# 15 0x0000000000ebfecd: '' +# 16 0x0000000002bdcfdd: '' +# 17 0x0000000002be1436: '' +# 18 0x0000000002be2b21: '' +# 19 0x0000000002be2e86: '' +# 20 0x0000000001125d89: '' +# 21 0x0000000002c82d8f: '' +# 22 0x0000000002cd6907: '' +# 23 0x0000000002c997f7: '' +# 24 0x0000000002c99ad9: '' +# 25 0x0000000002a9bfdd: '' +# 26 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:17:46 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:19:28 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d872e: '' +# 4 0x00000000010d887b: '' +# 5 0x00000000010d96f4: '' +# 6 0x000000000061ce93: '' +# 7 0x000000000062a516: '' +# 8 0x00007fefec49a00a: '../testbench/testbench-linux.sv:536' +# 9 0x000000000276f58a: '' +# 10 0x0000000000554abb: '' +# 11 0x00000000006e7153: '' +# 12 0x0000000000c01b55: '' +# 13 0x0000000000c069ab: '' +# 14 0x0000000000c0828e: '' +# 15 0x0000000000ebfecd: '' +# 16 0x0000000002bdcfdd: '' +# 17 0x0000000002be1436: '' +# 18 0x0000000002be2b21: '' +# 19 0x0000000002be2e86: '' +# 20 0x0000000001125d89: '' +# 21 0x0000000002c82d8f: '' +# 22 0x0000000002cd6907: '' +# 23 0x0000000002c997f7: '' +# 24 0x0000000002c99ad9: '' +# 25 0x0000000002a9bfdd: '' +# 26 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:19:28 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:21:11 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d872e: '' +# 4 0x00000000010d887b: '' +# 5 0x00000000010d96f4: '' +# 6 0x000000000061ce93: '' +# 7 0x000000000062a516: '' +# 8 0x00007fefec49a00a: '../testbench/testbench-linux.sv:536' +# 9 0x000000000276f58a: '' +# 10 0x0000000000554abb: '' +# 11 0x00000000006e7153: '' +# 12 0x0000000000c01b55: '' +# 13 0x0000000000c069ab: '' +# 14 0x0000000000c0828e: '' +# 15 0x0000000000ebfecd: '' +# 16 0x0000000002bdcfdd: '' +# 17 0x0000000002be1436: '' +# 18 0x0000000002be2b21: '' +# 19 0x0000000002be2e86: '' +# 20 0x0000000001125d89: '' +# 21 0x0000000002c82d8f: '' +# 22 0x0000000002cd6907: '' +# 23 0x0000000002c997f7: '' +# 24 0x0000000002c99ad9: '' +# 25 0x0000000002a9bfdd: '' +# 26 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:21:11 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:22:31 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d872e: '' +# 4 0x00000000010d887b: '' +# 5 0x00000000010d96f4: '' +# 6 0x000000000061ce93: '' +# 7 0x000000000062a516: '' +# 8 0x00007fefec49a00a: '../testbench/testbench-linux.sv:536' +# 9 0x000000000276f58a: '' +# 10 0x0000000000554abb: '' +# 11 0x00000000006e7153: '' +# 12 0x0000000000c01b55: '' +# 13 0x0000000000c069ab: '' +# 14 0x0000000000c0828e: '' +# 15 0x0000000000ebfecd: '' +# 16 0x0000000002bdcfdd: '' +# 17 0x0000000002be1436: '' +# 18 0x0000000002be2b21: '' +# 19 0x0000000002be2e86: '' +# 20 0x0000000001125d89: '' +# 21 0x0000000002c82d8f: '' +# 22 0x0000000002cd6907: '' +# 23 0x0000000002c997f7: '' +# 24 0x0000000002c99ad9: '' +# 25 0x0000000002a9bfdd: '' +# 26 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:22:31 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:24:04 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d872e: '' +# 4 0x00000000010d887b: '' +# 5 0x00000000010d96f4: '' +# 6 0x000000000061ce93: '' +# 7 0x000000000062a516: '' +# 8 0x00007fefec49a00a: '../testbench/testbench-linux.sv:536' +# 9 0x000000000276f58a: '' +# 10 0x0000000000554abb: '' +# 11 0x00000000006e7153: '' +# 12 0x0000000000c01b55: '' +# 13 0x0000000000c069ab: '' +# 14 0x0000000000c0828e: '' +# 15 0x0000000000ebfecd: '' +# 16 0x0000000002bdcfdd: '' +# 17 0x0000000002be1436: '' +# 18 0x0000000002be2b21: '' +# 19 0x0000000002be2e86: '' +# 20 0x0000000001125d89: '' +# 21 0x0000000002c82d8f: '' +# 22 0x0000000002cd6907: '' +# 23 0x0000000002c997f7: '' +# 24 0x0000000002c99ad9: '' +# 25 0x0000000002a9bfdd: '' +# 26 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:24:04 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:37:14 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d872e: '' +# 4 0x00000000010d887b: '' +# 5 0x00000000010d96f4: '' +# 6 0x000000000061ce93: '' +# 7 0x000000000062a516: '' +# 8 0x00007fefec49a00a: '../testbench/testbench-linux.sv:537' +# 9 0x000000000276f58a: '' +# 10 0x0000000000554abb: '' +# 11 0x00000000006e7153: '' +# 12 0x0000000000c01b55: '' +# 13 0x0000000000c069ab: '' +# 14 0x0000000000c0828e: '' +# 15 0x0000000000ebfecd: '' +# 16 0x0000000002bdcfdd: '' +# 17 0x0000000002be1436: '' +# 18 0x0000000002be2b21: '' +# 19 0x0000000002be2e86: '' +# 20 0x0000000001125d89: '' +# 21 0x0000000002c82d8f: '' +# 22 0x0000000002cd6907: '' +# 23 0x0000000002c997f7: '' +# 24 0x0000000002c99ad9: '' +# 25 0x0000000002a9bfdd: '' +# 26 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:37:14 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:39:03 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d872e: '' +# 4 0x00000000010d887b: '' +# 5 0x00000000010d96f4: '' +# 6 0x000000000061ce93: '' +# 7 0x000000000062a516: '' +# 8 0x00007fefec49a01a: '../testbench/testbench-linux.sv:538' +# 9 0x000000000276f58a: '' +# 10 0x0000000000554abb: '' +# 11 0x00000000006e7153: '' +# 12 0x0000000000c01b55: '' +# 13 0x0000000000c069ab: '' +# 14 0x0000000000c0828e: '' +# 15 0x0000000000ebfecd: '' +# 16 0x0000000002bdcfdd: '' +# 17 0x0000000002be1436: '' +# 18 0x0000000002be2b21: '' +# 19 0x0000000002be2e86: '' +# 20 0x0000000001125d89: '' +# 21 0x0000000002c82d8f: '' +# 22 0x0000000002cd6907: '' +# 23 0x0000000002c997f7: '' +# 24 0x0000000002c99ad9: '' +# 25 0x0000000002a9bfdd: '' +# 26 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:39:03 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:40:53 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d872e: '' +# 4 0x00000000010d887b: '' +# 5 0x00000000010d96f4: '' +# 6 0x000000000061ce93: '' +# 7 0x000000000062a516: '' +# 8 0x00007fefec49a04a: '../testbench/testbench-linux.sv:541' +# 9 0x000000000276f58a: '' +# 10 0x0000000000554abb: '' +# 11 0x00000000006e7153: '' +# 12 0x0000000000c01b55: '' +# 13 0x0000000000c069ab: '' +# 14 0x0000000000c0828e: '' +# 15 0x0000000000ebfecd: '' +# 16 0x0000000002bdcfdd: '' +# 17 0x0000000002be1436: '' +# 18 0x0000000002be2b21: '' +# 19 0x0000000002be2e86: '' +# 20 0x0000000001125d89: '' +# 21 0x0000000002c82d8f: '' +# 22 0x0000000002cd6907: '' +# 23 0x0000000002c997f7: '' +# 24 0x0000000002c99ad9: '' +# 25 0x0000000002a9bfdd: '' +# 26 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:40:53 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:42:30 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d872e: '' +# 4 0x00000000010d887b: '' +# 5 0x00000000010d96f4: '' +# 6 0x000000000061ce93: '' +# 7 0x000000000062a516: '' +# 8 0x00007fefec49a059: '../testbench/testbench-linux.sv:542' +# 9 0x000000000276f58a: '' +# 10 0x0000000000554abb: '' +# 11 0x00000000006e7153: '' +# 12 0x0000000000c01b55: '' +# 13 0x0000000000c069ab: '' +# 14 0x0000000000c0828e: '' +# 15 0x0000000000ebfecd: '' +# 16 0x0000000002bdcfdd: '' +# 17 0x0000000002be1436: '' +# 18 0x0000000002be2b21: '' +# 19 0x0000000002be2e86: '' +# 20 0x0000000001125d89: '' +# 21 0x0000000002c82d8f: '' +# 22 0x0000000002cd6907: '' +# 23 0x0000000002c997f7: '' +# 24 0x0000000002c99ad9: '' +# 25 0x0000000002a9bfdd: '' +# 26 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:42:30 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:43:39 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d872e: '' +# 4 0x00000000010d887b: '' +# 5 0x00000000010d96f4: '' +# 6 0x000000000061ce93: '' +# 7 0x000000000062a516: '' +# 8 0x00007fefec49a059: '../testbench/testbench-linux.sv:542' +# 9 0x000000000276f58a: '' +# 10 0x0000000000554abb: '' +# 11 0x00000000006e7153: '' +# 12 0x0000000000c01b55: '' +# 13 0x0000000000c069ab: '' +# 14 0x0000000000c0828e: '' +# 15 0x0000000000ebfecd: '' +# 16 0x0000000002bdcfdd: '' +# 17 0x0000000002be1436: '' +# 18 0x0000000002be2b21: '' +# 19 0x0000000002be2e86: '' +# 20 0x0000000001125d89: '' +# 21 0x0000000002c82d8f: '' +# 22 0x0000000002cd6907: '' +# 23 0x0000000002c997f7: '' +# 24 0x0000000002c99ad9: '' +# 25 0x0000000002a9bfdd: '' +# 26 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:43:39 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:44:37 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d8b44: '' +# 4 0x00000000010d8bac: '' +# 5 0x00000000010cef65: '' +# 6 0x00000000010d12f0: '' +# 7 0x00000000010d4700: '' +# 8 0x00000000007cded8: '' +# 9 0x0000000000809da8: '' +# 10 0x000000000081d399: '' +# 11 0x00000000007cb83e: '' +# 12 0x00007fefec49a035: '../testbench/testbench-linux.sv:543' +# 13 0x000000000276f58a: '' +# 14 0x0000000000554abb: '' +# 15 0x00000000006e7153: '' +# 16 0x0000000000c01b55: '' +# 17 0x0000000000c069ab: '' +# 18 0x0000000000c0828e: '' +# 19 0x0000000000ebfecd: '' +# 20 0x0000000002bdcfdd: '' +# 21 0x0000000002be1436: '' +# 22 0x0000000002be2b21: '' +# 23 0x0000000002be2e86: '' +# 24 0x0000000001125d89: '' +# 25 0x0000000002c82d8f: '' +# 26 0x0000000002cd6907: '' +# 27 0x0000000002c997f7: '' +# 28 0x0000000002c99ad9: '' +# 29 0x0000000002a9bfdd: '' +# 30 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:44:37 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:47:43 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d872e: '' +# 4 0x00000000010d887b: '' +# 5 0x00000000010d96f4: '' +# 6 0x000000000061ce93: '' +# 7 0x000000000062a516: '' +# 8 0x00007fefec49a059: '../testbench/testbench-linux.sv:542' +# 9 0x000000000276f58a: '' +# 10 0x0000000000554abb: '' +# 11 0x00000000006e7153: '' +# 12 0x0000000000c01b55: '' +# 13 0x0000000000c069ab: '' +# 14 0x0000000000c0828e: '' +# 15 0x0000000000ebfecd: '' +# 16 0x0000000002bdcfdd: '' +# 17 0x0000000002be1436: '' +# 18 0x0000000002be2b21: '' +# 19 0x0000000002be2e86: '' +# 20 0x0000000001125d89: '' +# 21 0x0000000002c82d8f: '' +# 22 0x0000000002cd6907: '' +# 23 0x0000000002c997f7: '' +# 24 0x0000000002c99ad9: '' +# 25 0x0000000002a9bfdd: '' +# 26 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:47:43 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + diff --git a/wally-pipelined/regression/wally-busybear.do b/wally-pipelined/regression/wally-busybear.do index 11876dde..0be7fcdd 100644 --- a/wally-pipelined/regression/wally-busybear.do +++ b/wally-pipelined/regression/wally-busybear.do @@ -35,7 +35,7 @@ vopt +acc work.testbench -o workopt vsim workopt -suppress 8852,12070 -do ./wave-dos/linux-waves.do +#do ./wave-dos/linux-waves.do #-- Run the Simulation diff --git a/wally-pipelined/src/privileged/csr.sv b/wally-pipelined/src/privileged/csr.sv index ae192e4d..d29104fc 100644 --- a/wally-pipelined/src/privileged/csr.sv +++ b/wally-pipelined/src/privileged/csr.sv @@ -39,7 +39,7 @@ module csr #(parameter input logic InterruptM, input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, uretM, input logic TimerIntM, ExtIntM, SwIntM, - input logic [63:0] MTIME, MTIMECMP, + input logic [63:0] MTIME_CLINT, MTIMECMP_CLINT, input logic InstrValidW, FloatRegWriteW, LoadStallD, input logic BPPredDirWrongM, input logic BTBPredPCWrongM, diff --git a/wally-pipelined/src/privileged/csrc.sv b/wally-pipelined/src/privileged/csrc.sv index f1cb9e0b..c762ea8c 100644 --- a/wally-pipelined/src/privileged/csrc.sv +++ b/wally-pipelined/src/privileged/csrc.sv @@ -30,8 +30,8 @@ // Ben 06/17/21: I brought in MTIME, MTIMECMP from CLINT. *** this probably isn't perfect though because it doesn't yet provide the ability to change these through CSR writes; overall this whole thing might need some rethinking module csrc #(parameter MCYCLE = 12'hB00, - MTIMEadr = 12'hB01, // address not specified in privileged spec. Consider moving to CLINT to match SiFive - MTIMECMPadr = 12'hB21, // not specified in privileged spec. Move to CLINT + MTIME = 12'hB01, // address not specified in privileged spec. Consider moving to CLINT to match SiFive + MTIMECMP = 12'hB21, // not specified in privileged spec. Move to CLINT MINSTRET = 12'hB02, MHPMCOUNTERBASE = 12'hB00, //MHPMCOUNTER3 = 12'hB03, @@ -39,8 +39,8 @@ module csrc #(parameter // ... more counters //MHPMCOUNTER31 = 12'hB1F, MCYCLEH = 12'hB80, - MTIMEHadr = 12'hB81, // address not specified in privileged spec. Consider moving to CLINT to match SiFive - MTIMECMPHadr = 12'hBA1, // not specified in privileged spec. Move to CLINT + MTIMEH = 12'hB81, // address not specified in privileged spec. Consider moving to CLINT to match SiFive + MTIMECMPH = 12'hBA1, // not specified in privileged spec. Move to CLINT MINSTRETH = 12'hB82, MHPMCOUNTERHBASE = 12'hB80, //MHPMCOUNTER3H = 12'hB83, @@ -82,7 +82,7 @@ module csrc #(parameter input logic [1:0] PrivilegeModeW, input logic [`XLEN-1:0] CSRWriteValM, input logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW, - input logic [63:0] MTIME, MTIMECMP, + input logic [63:0] MTIME_CLINT, MTIMECMP_CLINT, output logic [`XLEN-1:0] CSRCReadValM, output logic IllegalCSRCAccessM ); @@ -230,13 +230,13 @@ module csrc #(parameter if (CSRAdrM >= MHPMCOUNTERBASE+3 && CSRAdrM < MHPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CSRAdrM-MHPMCOUNTERBASE]; else if (CSRAdrM >= HPMCOUNTERBASE+3 && CSRAdrM < HPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CSRAdrM-HPMCOUNTERBASE]; else case (CSRAdrM) - MTIMEadr: CSRCReadValM = MTIME; - MTIMECMPadr: CSRCReadValM = MTIMECMP; + MTIME: CSRCReadValM = MTIME_CLINT; + MTIMECMP: CSRCReadValM = MTIMECMP_CLINT; MCYCLE: CSRCReadValM = CYCLE_REGW; MINSTRET: CSRCReadValM = INSTRET_REGW; //MHPMCOUNTER3: CSRCReadValM = HPMCOUNTER3_REGW; //MHPMCOUNTER4: CSRCReadValM = HPMCOUNTER4_REGW; - TIME: CSRCReadValM = MTIME; + TIME: CSRCReadValM = MTIME_CLINT; CYCLE: CSRCReadValM = CYCLE_REGW; INSTRET: CSRCReadValM = INSTRET_REGW; //HPMCOUNTER3: CSRCReadValM = HPMCOUNTER3_REGW; @@ -259,24 +259,24 @@ module csrc #(parameter else if (CSRAdrM >= MHPMCOUNTERHBASE+3 && CSRAdrM < MHPMCOUNTERHBASE+`COUNTERS) CSRCReadValM = HPMCOUNTERH_REGW[CSRAdrM-MHPMCOUNTERHBASE]; else if (CSRAdrM >= HPMCOUNTERHBASE+3 && CSRAdrM < HPMCOUNTERHBASE+`COUNTERS) CSRCReadValM = HPMCOUNTERH_REGW[CSRAdrM-HPMCOUNTERHBASE]; else case (CSRAdrM) - MTIMEadr: CSRCReadValM = MTIME[31:0]; - MTIMECMPadr: CSRCReadValM = MTIMECMP[31:0]; + MTIME: CSRCReadValM = MTIME_CLINT[31:0]; + MTIMECMP: CSRCReadValM = MTIMECMP_CLINT[31:0]; MCYCLE: CSRCReadValM = CYCLE_REGW[31:0]; MINSTRET: CSRCReadValM = INSTRET_REGW[31:0]; //MHPMCOUNTER3: CSRCReadValM = HPMCOUNTER3_REGW[31:0]; //MHPMCOUNTER4: CSRCReadValM = HPMCOUNTER4_REGW[31:0]; - TIME: CSRCReadValM = MTIME[31:0]; + TIME: CSRCReadValM = MTIME_CLINT[31:0]; CYCLE: CSRCReadValM = CYCLE_REGW[31:0]; INSTRET: CSRCReadValM = INSTRET_REGW[31:0]; //HPMCOUNTER3: CSRCReadValM = HPMCOUNTER3_REGW[31:0]; //HPMCOUNTER4: CSRCReadValM = HPMCOUNTER4_REGW[31:0]; - MTIMEHadr: CSRCReadValM = MTIME[63:32]; - MTIMECMPHadr: CSRCReadValM = MTIMECMP[63:32]; + MTIMEH: CSRCReadValM = MTIME_CLINT[63:32]; + MTIMECMPH: CSRCReadValM = MTIMECMP_CLINT[63:32]; MCYCLEH: CSRCReadValM = CYCLE_REGW[63:32]; MINSTRETH: CSRCReadValM = INSTRET_REGW[63:32]; //MHPMCOUNTER3H: CSRCReadValM = HPMCOUNTER3_REGW[63:32]; //MHPMCOUNTER4H: CSRCReadValM = HPMCOUNTER4_REGW[63:32]; - TIMEH: CSRCReadValM = MTIME[63:32]; + TIMEH: CSRCReadValM = MTIME_CLINT[63:32]; CYCLEH: CSRCReadValM = CYCLE_REGW[63:32]; INSTRETH: CSRCReadValM = INSTRET_REGW[63:32]; //HPMCOUNTER3H: CSRCReadValM = HPMCOUNTER3_REGW[63:32]; diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv index 839bae94..061b6a37 100644 --- a/wally-pipelined/src/privileged/privileged.sv +++ b/wally-pipelined/src/privileged/privileged.sv @@ -52,7 +52,7 @@ module privileged ( input logic LoadMisalignedFaultM, input logic StoreMisalignedFaultM, input logic TimerIntM, ExtIntM, SwIntM, - input logic [63:0] MTIME, MTIMECMP, + input logic [63:0] MTIME_CLINT, MTIMECMP_CLINT, input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM, input logic [4:0] SetFflagsM, diff --git a/wally-pipelined/src/uncore/uncore.sv b/wally-pipelined/src/uncore/uncore.sv index af9f6b6b..fb848376 100644 --- a/wally-pipelined/src/uncore/uncore.sv +++ b/wally-pipelined/src/uncore/uncore.sv @@ -58,7 +58,7 @@ module uncore ( output logic [31:0] GPIOPinsOut, GPIOPinsEn, input logic UARTSin, output logic UARTSout, - output logic [63:0] MTIME, MTIMECMP + output logic [63:0] MTIME_CLINT, MTIMECMP_CLINT ); logic [`XLEN-1:0] HWDATA; @@ -76,17 +76,6 @@ module uncore ( // unswizzle HSEL signals assign {HSELBootTim, HSELTim, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC} = HSELRegions; - /* PMA checker now handles decoding addresses. *** This can be deleted. - // AHB Address decoder - adrdec timdec(HADDR, `TIMBASE, `TIMRANGE, HSELTim); - adrdec boottimdec(HADDR, `BOOTTIMBASE, `BOOTTIMRANGE, HSELBootTim); - adrdec clintdec(HADDR, `CLINTBASE, `CLINTRANGE, HSELCLINT); - adrdec plicdec(HADDR, `PLICBASE, `PLICRANGE, HSELPLIC); - adrdec gpiodec(HADDR, `GPIOBASE, `GPIORANGE, HSELGPIO); - adrdec uartdec(HADDR, `UARTBASE, `UARTRANGE, PreHSELUART); - assign HSELUART = PreHSELUART && (HSIZE == 3'b000); // only byte writes to UART are supported - */ - // subword accesses: converts HWDATAIN to HWDATA subwordwrite sww(.*); @@ -95,7 +84,7 @@ module uncore ( dtim #(.BASE(`BOOTTIMBASE), .RANGE(`BOOTTIMRANGE)) bootdtim(.HSELTim(HSELBootTim), .HREADTim(HREADBootTim), .HRESPTim(HRESPBootTim), .HREADYTim(HREADYBootTim), .*); // memory-mapped I/O peripherals - clint clint(.HADDR(HADDR[15:0]), .*); + clint clint(.HADDR(HADDR[15:0]), .MTIME(MTIME_CLINT), .MTIMECMP(MTIMECMP_CLINT), .*); plic plic(.HADDR(HADDR[27:0]), .*); gpio gpio(.HADDR(HADDR[7:0]), .*); // *** may want to add GPIO interrupts uart uart(.HADDR(HADDR[2:0]), .TXRDYb(), .RXRDYb(), .INTR(UARTIntr), .SIN(UARTSin), .SOUT(UARTSout), diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 9cc8058a..2535eef3 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -34,7 +34,7 @@ module wallypipelinedhart ( input logic TimerIntM, ExtIntM, SwIntM, input logic InstrAccessFaultF, input logic DataAccessFaultM, - input logic [63:0] MTIME, MTIMECMP, + input logic [63:0] MTIME_CLINT, MTIMECMP_CLINT, // Bus Interface input logic [15:0] rd2, // bogus, delete when real multicycle fetch works input logic [`AHBW-1:0] HRDATA, diff --git a/wally-pipelined/src/wally/wallypipelinedsoc.sv b/wally-pipelined/src/wally/wallypipelinedsoc.sv index bde2eb2b..c85f5d4f 100644 --- a/wally-pipelined/src/wally/wallypipelinedsoc.sv +++ b/wally-pipelined/src/wally/wallypipelinedsoc.sv @@ -63,7 +63,7 @@ module wallypipelinedsoc ( logic [5:0] HSELRegions; logic InstrAccessFaultF, DataAccessFaultM; logic TimerIntM, SwIntM; // from CLINT - logic [63:0] MTIME, MTIMECMP; // from CLINT to CSRs + logic [63:0] MTIME_CLINT, MTIMECMP_CLINT; // from CLINT to CSRs logic ExtIntM; // from PLIC logic [2:0] HADDRD; logic [3:0] HSIZED; diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv index 0ca22608..c3c84de2 100644 --- a/wally-pipelined/testbench/testbench-busybear.sv +++ b/wally-pipelined/testbench/testbench-busybear.sv @@ -493,7 +493,12 @@ module testbench(); end scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext); PCtext2 = ""; + $display("loading tests"); + $display("PCtext = %s\n", PCtext); while (PCtext2 != "***") begin + $display("debugging\n"); + $display("PCtext is %s\n", PCtext); + $display("PCtext %s PCtext2 %s\n", PCtext, PCtext2); PCtext = {PCtext, " ", PCtext2}; scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext2); end diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv index 6cf20e67..9f80a33d 100644 --- a/wally-pipelined/testbench/testbench-linux.sv +++ b/wally-pipelined/testbench/testbench-linux.sv @@ -494,11 +494,14 @@ module testbench(); logic [31:0] InstrMask; logic forcedInstr; logic [63:0] lastPCD; + always @(dut.hart.ifu.PCD or dut.hart.ifu.InstrRawD or reset or negedge dut.hart.ifu.StallE) begin if(~HWRITE) begin #2; + $display("test point"); if (~reset && dut.hart.ifu.InstrRawD[15:0] !== {16{1'bx}} && dut.hart.ifu.PCD !== 64'h0 && ~dut.hart.ifu.StallE) begin if (dut.hart.ifu.PCD !== lastPCD) begin + $display("tp2"); lastCheckInstrD = CheckInstrD; lastPC <= dut.hart.ifu.PCD; lastPC2 <= lastPC; @@ -525,16 +528,22 @@ module testbench(); end end else begin + $display("tp4"); if($feof(data_file_PC)) begin $display("no more PC data to read"); `ERROR end scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtextD); PCtext2 = ""; + $display("tp5 PCtextD = %s PCtext2 = %s\n", PCtextD, PCtext2); while (PCtext2 != "***") begin + $display("tp6 PCtextD = %s PCtext2 = %s\n", PCtextD, PCtext2); PCtextD = {PCtextD, " ", PCtext2}; + $display("tp8"); scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext2); + $display("tp9"); end + $display("tp7 PCtextD = %s PCtext2 = %s\n", PCtextD, PCtext2); scan_file_PC = $fscanf(data_file_PC, "%x\n", CheckInstrD); if(dut.hart.ifu.PCD === pcExpected) begin if((dut.hart.ifu.InstrRawD[6:0] == 7'b1010011) || // for now, NOP out any float instrs @@ -607,6 +616,7 @@ module testbench(); end end + // Track names of instructions string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; logic [31:0] InstrW; From 35c74348a41e3d8e51eb2d453d43903c4fd3946a Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 18 Jun 2021 08:05:50 -0400 Subject: [PATCH 3/8] allow all size memory access in CLINT; added underscore to peripheral address symbols --- .../config/buildroot/wally-config.vh | 40 +++++++++---------- .../config/busybear/wally-config.vh | 40 +++++++++---------- .../config/coremark-64i/wally-config.vh | 40 +++++++++---------- .../config/coremark/wally-config.vh | 40 +++++++++---------- .../config/coremark_bare/wally-config.vh | 40 +++++++++---------- wally-pipelined/config/rv32ic/wally-config.vh | 40 +++++++++---------- wally-pipelined/config/rv64BP/wally-config.vh | 40 +++++++++---------- wally-pipelined/config/rv64ic/wally-config.vh | 40 +++++++++---------- .../config/rv64icfd/wally-config.vh | 40 +++++++++---------- .../config/rv64imc/wally-config.vh | 40 +++++++++---------- wally-pipelined/src/mmu/pmachecker.sv | 17 +++----- wally-pipelined/src/uncore/imem.sv | 16 ++++---- wally-pipelined/src/uncore/uncore.sv | 4 +- .../testbench/testbench-imperas.sv | 8 ++-- .../testbench/testbench-privileged.sv | 4 +- 15 files changed, 222 insertions(+), 227 deletions(-) diff --git a/wally-pipelined/config/buildroot/wally-config.vh b/wally-pipelined/config/buildroot/wally-config.vh index 065a6ebc..c5469e35 100644 --- a/wally-pipelined/config/buildroot/wally-config.vh +++ b/wally-pipelined/config/buildroot/wally-config.vh @@ -61,26 +61,26 @@ // Peripheral Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define BOOTTIMSUPPORTED 1'b1 -`define BOOTTIMBASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -`define BOOTTIMRANGE 32'h00003FFF -//`define BOOTTIMBASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -//`define BOOTTIMRANGE 32'h00000FFF -`define TIMSUPPORTED 1'b1 -`define TIMBASE 32'h80000000 -`define TIMRANGE 32'h07FFFFFF -`define CLINTSUPPORTED 1'b1 -`define CLINTBASE 32'h02000000 -`define CLINTRANGE 32'h0000FFFF -`define GPIOSUPPORTED 1'b1 -`define GPIOBASE 32'h10012000 -`define GPIORANGE 32'h000000FF -`define UARTSUPPORTED 1'b1 -`define UARTBASE 32'h10000000 -`define UARTRANGE 32'h00000007 -`define PLICSUPPORTED 1'b1 -`define PLICBASE 32'h0C000000 -`define PLICRANGE 32'h03FFFFFF +`define BOOTTIM_SUPPORTED 1'b1 +`define BOOTTIM_BASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +`define BOOTTIM_RANGE 32'h00003FFF +//`define BOOTTIM_BASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +//`define BOOTTIM_RANGE 32'h00000FFF +`define TIM_SUPPORTED 1'b1 +`define TIM_BASE 32'h80000000 +`define TIM_RANGE 32'h07FFFFFF +`define CLINT_SUPPORTED 1'b1 +`define CLINT_BASE 32'h02000000 +`define CLINT_RANGE 32'h0000FFFF +`define GPIO_SUPPORTED 1'b1 +`define GPIO_BASE 32'h10012000 +`define GPIO_RANGE 32'h000000FF +`define UART_SUPPORTED 1'b1 +`define UART_BASE 32'h10000000 +`define UART_RANGE 32'h00000007 +`define PLIC_SUPPORTED 1'b1 +`define PLIC_BASE 32'h0C000000 +`define PLIC_RANGE 32'h03FFFFFF // Bus Interface width `define AHBW 64 diff --git a/wally-pipelined/config/busybear/wally-config.vh b/wally-pipelined/config/busybear/wally-config.vh index da7db228..516ebcae 100644 --- a/wally-pipelined/config/busybear/wally-config.vh +++ b/wally-pipelined/config/busybear/wally-config.vh @@ -62,26 +62,26 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define BOOTTIMSUPPORTED 1'b1 -`define BOOTTIMBASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -`define BOOTTIMRANGE 32'h00003FFF -//`define BOOTTIMBASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -//`define BOOTTIMRANGE 32'h00000FFF -`define TIMSUPPORTED 1'b1 -`define TIMBASE 32'h80000000 -`define TIMRANGE 32'h07FFFFFF -`define CLINTSUPPORTED 1'b1 -`define CLINTBASE 32'h02000000 -`define CLINTRANGE 32'h0000FFFF -`define GPIOSUPPORTED 1'b1 -`define GPIOBASE 32'h10012000 -`define GPIORANGE 32'h000000FF -`define UARTSUPPORTED 1'b1 -`define UARTBASE 32'h10000000 -`define UARTRANGE 32'h00000007 -`define PLICSUPPORTED 1'b1 -`define PLICBASE 32'h0C000000 -`define PLICRANGE 32'h03FFFFFF +`define BOOTTIM_SUPPORTED 1'b1 +`define BOOTTIM_BASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +`define BOOTTIM_RANGE 32'h00003FFF +//`define BOOTTIM_BASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +//`define BOOTTIM_RANGE 32'h00000FFF +`define TIM_SUPPORTED 1'b1 +`define TIM_BASE 32'h80000000 +`define TIM_RANGE 32'h07FFFFFF +`define CLINT_SUPPORTED 1'b1 +`define CLINT_BASE 32'h02000000 +`define CLINT_RANGE 32'h0000FFFF +`define GPIO_SUPPORTED 1'b1 +`define GPIO_BASE 32'h10012000 +`define GPIO_RANGE 32'h000000FF +`define UART_SUPPORTED 1'b1 +`define UART_BASE 32'h10000000 +`define UART_RANGE 32'h00000007 +`define PLIC_SUPPORTED 1'b1 +`define PLIC_BASE 32'h0C000000 +`define PLIC_RANGE 32'h03FFFFFF // Bus Interface width `define AHBW 64 diff --git a/wally-pipelined/config/coremark-64i/wally-config.vh b/wally-pipelined/config/coremark-64i/wally-config.vh index 848cb3bc..f72b4f61 100644 --- a/wally-pipelined/config/coremark-64i/wally-config.vh +++ b/wally-pipelined/config/coremark-64i/wally-config.vh @@ -54,26 +54,26 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define BOOTTIMSUPPORTED 1'b1 -`define BOOTTIMBASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -`define BOOTTIMRANGE 32'h00003FFF -//`define BOOTTIMBASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -//`define BOOTTIMRANGE 32'h00000FFF -`define TIMSUPPORTED 1'b1 -`define TIMBASE 32'h80000000 -`define TIMRANGE 32'h07FFFFFF -`define CLINTSUPPORTED 1'b1 -`define CLINTBASE 32'h02000000 -`define CLINTRANGE 32'h0000FFFF -`define GPIOSUPPORTED 1'b1 -`define GPIOBASE 32'h10012000 -`define GPIORANGE 32'h000000FF -`define UARTSUPPORTED 1'b1 -`define UARTBASE 32'h10000000 -`define UARTRANGE 32'h00000007 -`define PLICSUPPORTED 1'b1 -`define PLICBASE 32'h0C000000 -`define PLICRANGE 32'h03FFFFFF +`define BOOTTIM_SUPPORTED 1'b1 +`define BOOTTIM_BASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +`define BOOTTIM_RANGE 32'h00003FFF +//`define BOOTTIM_BASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +//`define BOOTTIM_RANGE 32'h00000FFF +`define TIM_SUPPORTED 1'b1 +`define TIM_BASE 32'h80000000 +`define TIM_RANGE 32'h07FFFFFF +`define CLINT_SUPPORTED 1'b1 +`define CLINT_BASE 32'h02000000 +`define CLINT_RANGE 32'h0000FFFF +`define GPIO_SUPPORTED 1'b1 +`define GPIO_BASE 32'h10012000 +`define GPIO_RANGE 32'h000000FF +`define UART_SUPPORTED 1'b1 +`define UART_BASE 32'h10000000 +`define UART_RANGE 32'h00000007 +`define PLIC_SUPPORTED 1'b1 +`define PLIC_BASE 32'h0C000000 +`define PLIC_RANGE 32'h03FFFFFF // Test modes diff --git a/wally-pipelined/config/coremark/wally-config.vh b/wally-pipelined/config/coremark/wally-config.vh index 615e1802..13d364dd 100644 --- a/wally-pipelined/config/coremark/wally-config.vh +++ b/wally-pipelined/config/coremark/wally-config.vh @@ -62,26 +62,26 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define BOOTTIMSUPPORTED 1'b1 -`define BOOTTIMBASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -`define BOOTTIMRANGE 32'h00003FFF -//`define BOOTTIMBASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -//`define BOOTTIMRANGE 32'h00000FFF -`define TIMSUPPORTED 1'b1 -`define TIMBASE 32'h80000000 -`define TIMRANGE 32'h07FFFFFF -`define CLINTSUPPORTED 1'b1 -`define CLINTBASE 32'h02000000 -`define CLINTRANGE 32'h0000FFFF -`define GPIOSUPPORTED 1'b1 -`define GPIOBASE 32'h10012000 -`define GPIORANGE 32'h000000FF -`define UARTSUPPORTED 1'b1 -`define UARTBASE 32'h10000000 -`define UARTRANGE 32'h00000007 -`define PLICSUPPORTED 1'b1 -`define PLICBASE 32'h0C000000 -`define PLICRANGE 32'h03FFFFFF +`define BOOTTIM_SUPPORTED 1'b1 +`define BOOTTIM_BASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +`define BOOTTIM_RANGE 32'h00003FFF +//`define BOOTTIM_BASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +//`define BOOTTIM_RANGE 32'h00000FFF +`define TIM_SUPPORTED 1'b1 +`define TIM_BASE 32'h80000000 +`define TIM_RANGE 32'h07FFFFFF +`define CLINT_SUPPORTED 1'b1 +`define CLINT_BASE 32'h02000000 +`define CLINT_RANGE 32'h0000FFFF +`define GPIO_SUPPORTED 1'b1 +`define GPIO_BASE 32'h10012000 +`define GPIO_RANGE 32'h000000FF +`define UART_SUPPORTED 1'b1 +`define UART_BASE 32'h10000000 +`define UART_RANGE 32'h00000007 +`define PLIC_SUPPORTED 1'b1 +`define PLIC_BASE 32'h0C000000 +`define PLIC_RANGE 32'h03FFFFFF // Test modes diff --git a/wally-pipelined/config/coremark_bare/wally-config.vh b/wally-pipelined/config/coremark_bare/wally-config.vh index 219e4225..5b62a23e 100644 --- a/wally-pipelined/config/coremark_bare/wally-config.vh +++ b/wally-pipelined/config/coremark_bare/wally-config.vh @@ -62,26 +62,26 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define BOOTTIMSUPPORTED 1'b1 -`define BOOTTIMBASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -`define BOOTTIMRANGE 32'h00003FFF -//`define BOOTTIMBASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -//`define BOOTTIMRANGE 32'h00000FFF -`define TIMSUPPORTED 1'b1 -`define TIMBASE 32'h80000000 -`define TIMRANGE 32'h07FFFFFF -`define CLINTSUPPORTED 1'b1 -`define CLINTBASE 32'h02000000 -`define CLINTRANGE 32'h0000FFFF -`define GPIOSUPPORTED 1'b1 -`define GPIOBASE 32'h10012000 -`define GPIORANGE 32'h000000FF -`define UARTSUPPORTED 1'b1 -`define UARTBASE 32'h10000000 -`define UARTRANGE 32'h00000007 -`define PLICSUPPORTED 1'b1 -`define PLICBASE 32'h0C000000 -`define PLICRANGE 32'h03FFFFFF +`define BOOTTIM_SUPPORTED 1'b1 +`define BOOTTIM_BASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +`define BOOTTIM_RANGE 32'h00003FFF +//`define BOOTTIM_BASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +//`define BOOTTIM_RANGE 32'h00000FFF +`define TIM_SUPPORTED 1'b1 +`define TIM_BASE 32'h80000000 +`define TIM_RANGE 32'h07FFFFFF +`define CLINT_SUPPORTED 1'b1 +`define CLINT_BASE 32'h02000000 +`define CLINT_RANGE 32'h0000FFFF +`define GPIO_SUPPORTED 1'b1 +`define GPIO_BASE 32'h10012000 +`define GPIO_RANGE 32'h000000FF +`define UART_SUPPORTED 1'b1 +`define UART_BASE 32'h10000000 +`define UART_RANGE 32'h00000007 +`define PLIC_SUPPORTED 1'b1 +`define PLIC_BASE 32'h0C000000 +`define PLIC_RANGE 32'h03FFFFFF // Test modes diff --git a/wally-pipelined/config/rv32ic/wally-config.vh b/wally-pipelined/config/rv32ic/wally-config.vh index 6f17e259..f6f1860a 100644 --- a/wally-pipelined/config/rv32ic/wally-config.vh +++ b/wally-pipelined/config/rv32ic/wally-config.vh @@ -61,26 +61,26 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define BOOTTIMSUPPORTED 1'b1 -`define BOOTTIMBASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -`define BOOTTIMRANGE 32'h00003FFF -//`define BOOTTIMBASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -//`define BOOTTIMRANGE 32'h00000FFF -`define TIMSUPPORTED 1'b1 -`define TIMBASE 32'h80000000 -`define TIMRANGE 32'h07FFFFFF -`define CLINTSUPPORTED 1'b1 -`define CLINTBASE 32'h02000000 -`define CLINTRANGE 32'h0000FFFF -`define GPIOSUPPORTED 1'b1 -`define GPIOBASE 32'h10012000 -`define GPIORANGE 32'h000000FF -`define UARTSUPPORTED 1'b1 -`define UARTBASE 32'h10000000 -`define UARTRANGE 32'h00000007 -`define PLICSUPPORTED 1'b1 -`define PLICBASE 32'h0C000000 -`define PLICRANGE 32'h03FFFFFF +`define BOOTTIM_SUPPORTED 1'b1 +`define BOOTTIM_BASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +`define BOOTTIM_RANGE 32'h00003FFF +//`define BOOTTIM_BASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +//`define BOOTTIM_RANGE 32'h00000FFF +`define TIM_SUPPORTED 1'b1 +`define TIM_BASE 32'h80000000 +`define TIM_RANGE 32'h07FFFFFF +`define CLINT_SUPPORTED 1'b1 +`define CLINT_BASE 32'h02000000 +`define CLINT_RANGE 32'h0000FFFF +`define GPIO_SUPPORTED 1'b1 +`define GPIO_BASE 32'h10012000 +`define GPIO_RANGE 32'h000000FF +`define UART_SUPPORTED 1'b1 +`define UART_BASE 32'h10000000 +`define UART_RANGE 32'h00000007 +`define PLIC_SUPPORTED 1'b1 +`define PLIC_BASE 32'h0C000000 +`define PLIC_RANGE 32'h03FFFFFF // Bus Interface width `define AHBW 32 diff --git a/wally-pipelined/config/rv64BP/wally-config.vh b/wally-pipelined/config/rv64BP/wally-config.vh index 0cf38f28..477055de 100644 --- a/wally-pipelined/config/rv64BP/wally-config.vh +++ b/wally-pipelined/config/rv64BP/wally-config.vh @@ -63,26 +63,26 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define BOOTTIMSUPPORTED 1'b1 -`define BOOTTIMBASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -`define BOOTTIMRANGE 32'h00003FFF -//`define BOOTTIMBASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -//`define BOOTTIMRANGE 32'h00000FFF -`define TIMSUPPORTED 1'b1 -`define TIMBASE 32'h80000000 -`define TIMRANGE 32'h07FFFFFF -`define CLINTSUPPORTED 1'b1 -`define CLINTBASE 32'h02000000 -`define CLINTRANGE 32'h0000FFFF -`define GPIOSUPPORTED 1'b1 -`define GPIOBASE 32'h10012000 -`define GPIORANGE 32'h000000FF -`define UARTSUPPORTED 1'b1 -`define UARTBASE 32'h10000000 -`define UARTRANGE 32'h00000007 -`define PLICSUPPORTED 1'b1 -`define PLICBASE 32'h0C000000 -`define PLICRANGE 32'h03FFFFFF +`define BOOTTIM_SUPPORTED 1'b1 +`define BOOTTIM_BASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +`define BOOTTIM_RANGE 32'h00003FFF +//`define BOOTTIM_BASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +//`define BOOTTIM_RANGE 32'h00000FFF +`define TIM_SUPPORTED 1'b1 +`define TIM_BASE 32'h80000000 +`define TIM_RANGE 32'h07FFFFFF +`define CLINT_SUPPORTED 1'b1 +`define CLINT_BASE 32'h02000000 +`define CLINT_RANGE 32'h0000FFFF +`define GPIO_SUPPORTED 1'b1 +`define GPIO_BASE 32'h10012000 +`define GPIO_RANGE 32'h000000FF +`define UART_SUPPORTED 1'b1 +`define UART_BASE 32'h10000000 +`define UART_RANGE 32'h00000007 +`define PLIC_SUPPORTED 1'b1 +`define PLIC_BASE 32'h0C000000 +`define PLIC_RANGE 32'h03FFFFFF // Test modes diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh index d9928cdb..32943165 100644 --- a/wally-pipelined/config/rv64ic/wally-config.vh +++ b/wally-pipelined/config/rv64ic/wally-config.vh @@ -65,26 +65,26 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define BOOTTIMSUPPORTED 1'b1 -`define BOOTTIMBASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -`define BOOTTIMRANGE 32'h00003FFF -//`define BOOTTIMBASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -//`define BOOTTIMRANGE 32'h00000FFF -`define TIMSUPPORTED 1'b1 -`define TIMBASE 32'h80000000 -`define TIMRANGE 32'h07FFFFFF -`define CLINTSUPPORTED 1'b1 -`define CLINTBASE 32'h02000000 -`define CLINTRANGE 32'h0000FFFF -`define GPIOSUPPORTED 1'b1 -`define GPIOBASE 32'h10012000 -`define GPIORANGE 32'h000000FF -`define UARTSUPPORTED 1'b1 -`define UARTBASE 32'h10000000 -`define UARTRANGE 32'h00000007 -`define PLICSUPPORTED 1'b1 -`define PLICBASE 32'h0C000000 -`define PLICRANGE 32'h03FFFFFF +`define BOOTTIM_SUPPORTED 1'b1 +`define BOOTTIM_BASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +`define BOOTTIM_RANGE 32'h00003FFF +//`define BOOTTIM_BASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +//`define BOOTTIM_RANGE 32'h00000FFF +`define TIM_SUPPORTED 1'b1 +`define TIM_BASE 32'h80000000 +`define TIM_RANGE 32'h07FFFFFF +`define CLINT_SUPPORTED 1'b1 +`define CLINT_BASE 32'h02000000 +`define CLINT_RANGE 32'h0000FFFF +`define GPIO_SUPPORTED 1'b1 +`define GPIO_BASE 32'h10012000 +`define GPIO_RANGE 32'h000000FF +`define UART_SUPPORTED 1'b1 +`define UART_BASE 32'h10000000 +`define UART_RANGE 32'h00000007 +`define PLIC_SUPPORTED 1'b1 +`define PLIC_BASE 32'h0C000000 +`define PLIC_RANGE 32'h03FFFFFF // Test modes diff --git a/wally-pipelined/config/rv64icfd/wally-config.vh b/wally-pipelined/config/rv64icfd/wally-config.vh index 20da468c..1a7df3c4 100644 --- a/wally-pipelined/config/rv64icfd/wally-config.vh +++ b/wally-pipelined/config/rv64icfd/wally-config.vh @@ -65,26 +65,26 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define BOOTTIMSUPPORTED 1'b1 -`define BOOTTIMBASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -`define BOOTTIMRANGE 32'h00003FFF -//`define BOOTTIMBASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -//`define BOOTTIMRANGE 32'h00000FFF -`define TIMSUPPORTED 1'b1 -`define TIMBASE 32'h80000000 -`define TIMRANGE 32'h07FFFFFF -`define CLINTSUPPORTED 1'b1 -`define CLINTBASE 32'h02000000 -`define CLINTRANGE 32'h0000FFFF -`define GPIOSUPPORTED 1'b1 -`define GPIOBASE 32'h10012000 -`define GPIORANGE 32'h000000FF -`define UARTSUPPORTED 1'b1 -`define UARTBASE 32'h10000000 -`define UARTRANGE 32'h00000007 -`define PLICSUPPORTED 1'b1 -`define PLICBASE 32'h0C000000 -`define PLICRANGE 32'h03FFFFFF +`define BOOTTIM_SUPPORTED 1'b1 +`define BOOTTIM_BASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +`define BOOTTIM_RANGE 32'h00003FFF +//`define BOOTTIM_BASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +//`define BOOTTIM_RANGE 32'h00000FFF +`define TIM_SUPPORTED 1'b1 +`define TIM_BASE 32'h80000000 +`define TIM_RANGE 32'h07FFFFFF +`define CLINT_SUPPORTED 1'b1 +`define CLINT_BASE 32'h02000000 +`define CLINT_RANGE 32'h0000FFFF +`define GPIO_SUPPORTED 1'b1 +`define GPIO_BASE 32'h10012000 +`define GPIO_RANGE 32'h000000FF +`define UART_SUPPORTED 1'b1 +`define UART_BASE 32'h10000000 +`define UART_RANGE 32'h00000007 +`define PLIC_SUPPORTED 1'b1 +`define PLIC_BASE 32'h0C000000 +`define PLIC_RANGE 32'h03FFFFFF // Test modes diff --git a/wally-pipelined/config/rv64imc/wally-config.vh b/wally-pipelined/config/rv64imc/wally-config.vh index 5e63f6da..b6f5ab9a 100644 --- a/wally-pipelined/config/rv64imc/wally-config.vh +++ b/wally-pipelined/config/rv64imc/wally-config.vh @@ -61,26 +61,26 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define BOOTTIMSUPPORTED 1'b1 -`define BOOTTIMBASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -`define BOOTTIMRANGE 32'h00003FFF -//`define BOOTTIMBASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -//`define BOOTTIMRANGE 32'h00000FFF -`define TIMSUPPORTED 1'b1 -`define TIMBASE 32'h80000000 -`define TIMRANGE 32'h07FFFFFF -`define CLINTSUPPORTED 1'b1 -`define CLINTBASE 32'h02000000 -`define CLINTRANGE 32'h0000FFFF -`define GPIOSUPPORTED 1'b1 -`define GPIOBASE 32'h10012000 -`define GPIORANGE 32'h000000FF -`define UARTSUPPORTED 1'b1 -`define UARTBASE 32'h10000000 -`define UARTRANGE 32'h00000007 -`define PLICSUPPORTED 1'b1 -`define PLICBASE 32'h0C000000 -`define PLICRANGE 32'h03FFFFFF +`define BOOTTIM_SUPPORTED 1'b1 +`define BOOTTIM_BASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +`define BOOTTIM_RANGE 32'h00003FFF +//`define BOOTTIM_BASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +//`define BOOTTIM_RANGE 32'h00000FFF +`define TIM_SUPPORTED 1'b1 +`define TIM_BASE 32'h80000000 +`define TIM_RANGE 32'h07FFFFFF +`define CLINT_SUPPORTED 1'b1 +`define CLINT_BASE 32'h02000000 +`define CLINT_RANGE 32'h0000FFFF +`define GPIO_SUPPORTED 1'b1 +`define GPIO_BASE 32'h10012000 +`define GPIO_RANGE 32'h000000FF +`define UART_SUPPORTED 1'b1 +`define UART_BASE 32'h10000000 +`define UART_RANGE 32'h00000007 +`define PLIC_SUPPORTED 1'b1 +`define PLIC_BASE 32'h0C000000 +`define PLIC_RANGE 32'h03FFFFFF // Test modes diff --git a/wally-pipelined/src/mmu/pmachecker.sv b/wally-pipelined/src/mmu/pmachecker.sv index b8ecc366..0aaa8b97 100644 --- a/wally-pipelined/src/mmu/pmachecker.sv +++ b/wally-pipelined/src/mmu/pmachecker.sv @@ -57,23 +57,18 @@ module pmachecker ( // Determine which region of physical memory (if any) is being accessed // *** linux tests fail early when Access is anything other than 1b1 - pmaadrdec boottimdec(HADDR, `BOOTTIMBASE, `BOOTTIMRANGE, `BOOTTIMSUPPORTED, 1'b1/*AccessRX*/, HSIZE, 4'b1111, HSELRegions[5]); - pmaadrdec timdec(HADDR, `TIMBASE, `TIMRANGE, `TIMSUPPORTED, 1'b1/*AccessRWX*/, HSIZE, 4'b1111, HSELRegions[4]); - pmaadrdec clintdec(HADDR, `CLINTBASE, `CLINTRANGE, `CLINTSUPPORTED, AccessRW, HSIZE, (`XLEN==64 ? 4'b1000 : 4'b0100), HSELRegions[3]); - pmaadrdec gpiodec(HADDR, `GPIOBASE, `GPIORANGE, `GPIOSUPPORTED, AccessRW, HSIZE, 4'b0100, HSELRegions[2]); - pmaadrdec uartdec(HADDR, `UARTBASE, `UARTRANGE, `UARTSUPPORTED, AccessRW, HSIZE, 4'b0001, HSELRegions[1]); - pmaadrdec plicdec(HADDR, `PLICBASE, `PLICRANGE, `PLICSUPPORTED, AccessRW, HSIZE, 4'b0100, HSELRegions[0]); + pmaadrdec boottimdec(HADDR, `BOOTTIM_BASE, `BOOTTIM_RANGE, `BOOTTIM_SUPPORTED, 1'b1/*AccessRX*/, HSIZE, 4'b1111, HSELRegions[5]); + pmaadrdec timdec(HADDR, `TIM_BASE, `TIM_RANGE, `TIM_SUPPORTED, 1'b1/*AccessRWX*/, HSIZE, 4'b1111, HSELRegions[4]); + pmaadrdec clintdec(HADDR, `CLINT_BASE, `CLINT_RANGE, `CLINT_SUPPORTED, AccessRW, HSIZE, 4'b1111, HSELRegions[3]); + pmaadrdec gpiodec(HADDR, `GPIO_BASE, `GPIO_RANGE, `GPIO_SUPPORTED, AccessRW, HSIZE, 4'b0100, HSELRegions[2]); + pmaadrdec uartdec(HADDR, `UART_BASE, `UART_RANGE, `UART_SUPPORTED, AccessRW, HSIZE, 4'b0001, HSELRegions[1]); + pmaadrdec plicdec(HADDR, `PLIC_BASE, `PLIC_RANGE, `PLIC_SUPPORTED, AccessRW, HSIZE, 4'b0100, HSELRegions[0]); // Only RAM memory regions are cacheable assign Cacheable = HSELRegions[5] | HSELRegions[4]; assign Idempotent = HSELRegions[4]; assign AtomicAllowed = HSELRegions[4]; - /*ExecuteAccessF | ReadAccessM | WriteAccessM; */ - - // Swizzle region bits - //assign HSELRegions = {BootTim, Tim, CLINT, GPIO, UART, PLIC}; - // Detect access faults assign PMAAccessFault = ~|HSELRegions; assign PMAInstrAccessFaultF = ExecuteAccessF && PMAAccessFault; diff --git a/wally-pipelined/src/uncore/imem.sv b/wally-pipelined/src/uncore/imem.sv index 6aaad598..85362edf 100644 --- a/wally-pipelined/src/uncore/imem.sv +++ b/wally-pipelined/src/uncore/imem.sv @@ -32,8 +32,8 @@ module imem ( output logic InstrAccessFaultF); /* verilator lint_off UNDRIVEN */ - logic [`XLEN-1:0] RAM[`TIMBASE>>(1+`XLEN/32):(`TIMRANGE+`TIMBASE)>>(1+`XLEN/32)]; - logic [`XLEN-1:0] bootram[`BOOTTIMBASE>>(1+`XLEN/32):(`BOOTTIMRANGE+`BOOTTIMBASE)>>(1+`XLEN/32)]; + logic [`XLEN-1:0] RAM[`TIM_BASE>>(1+`XLEN/32):(`TIM_RANGE+`TIM_BASE)>>(1+`XLEN/32)]; + logic [`XLEN-1:0] bootram[`BOOTTIM_BASE>>(1+`XLEN/32):(`BOOTTIM_RANGE+`BOOTTIM_BASE)>>(1+`XLEN/32)]; /* verilator lint_on UNDRIVEN */ logic [31:0] adrbits; // needs to be 32 bits to index RAM logic [`XLEN-1:0] rd; @@ -44,27 +44,27 @@ module imem ( else assign adrbits = AdrF[31:3]; endgenerate - assign #2 rd = (AdrF < (`TIMBASE >> 1)) ? bootram[adrbits] : RAM[adrbits]; // busybear: 2 memory options + assign #2 rd = (AdrF < (`TIM_BASE >> 1)) ? bootram[adrbits] : RAM[adrbits]; // busybear: 2 memory options // hack right now for unaligned 32-bit instructions // eventually this will need to cause a stall like a cache miss // when the instruction wraps around a cache line // could be optimized to only stall when the instruction wrapping is 32 bits - assign #2 rd2 = (AdrF < (`TIMBASE >> 1)) ? bootram[adrbits+1][15:0] : RAM[adrbits+1][15:0]; //busybear: 2 memory options + assign #2 rd2 = (AdrF < (`TIM_BASE >> 1)) ? bootram[adrbits+1][15:0] : RAM[adrbits+1][15:0]; //busybear: 2 memory options generate if (`XLEN==32) begin assign InstrF = AdrF[1] ? {rd2[15:0], rd[31:16]} : rd; // First, AdrF needs to get its last bit appended back onto it - // Then not-XORing it with TIMBASE checks if it matches TIMBASE exactly - // Then ORing it with TIMRANGE introduces some leeway into the previous check, by allowing the lower bits to be either high or low + // Then not-XORing it with TIM_BASE checks if it matches TIM_BASE exactly + // Then ORing it with TIM_RANGE introduces some leeway into the previous check, by allowing the lower bits to be either high or low - assign InstrAccessFaultF = (~&(({AdrF,1'b0} ~^ `TIMBASE) | `TIMRANGE)) & (~&(({AdrF,1'b0} ~^ `BOOTTIMBASE) | `BOOTTIMRANGE)); + assign InstrAccessFaultF = (~&(({AdrF,1'b0} ~^ `TIM_BASE) | `TIM_RANGE)) & (~&(({AdrF,1'b0} ~^ `BOOTTIM_BASE) | `BOOTTIM_RANGE)); end else begin assign InstrF = AdrF[2] ? (AdrF[1] ? {rd2[15:0], rd[63:48]} : rd[63:32]) : (AdrF[1] ? rd[47:16] : rd[31:0]); // - assign InstrAccessFaultF = (|AdrF[`XLEN-1:32] | ~&({AdrF[31:1],1'b0} ~^ `TIMBASE | `TIMRANGE)) & (|AdrF[`XLEN-1:32] | ~&({AdrF[31:1],1'b0} ~^ `BOOTTIMBASE | `BOOTTIMRANGE)); + assign InstrAccessFaultF = (|AdrF[`XLEN-1:32] | ~&({AdrF[31:1],1'b0} ~^ `TIM_BASE | `TIM_RANGE)) & (|AdrF[`XLEN-1:32] | ~&({AdrF[31:1],1'b0} ~^ `BOOTTIM_BASE | `BOOTTIM_RANGE)); end endgenerate endmodule diff --git a/wally-pipelined/src/uncore/uncore.sv b/wally-pipelined/src/uncore/uncore.sv index fb848376..d49414a7 100644 --- a/wally-pipelined/src/uncore/uncore.sv +++ b/wally-pipelined/src/uncore/uncore.sv @@ -80,8 +80,8 @@ module uncore ( subwordwrite sww(.*); // tightly integrated memory - dtim #(.BASE(`TIMBASE), .RANGE(`TIMRANGE)) dtim (.*); - dtim #(.BASE(`BOOTTIMBASE), .RANGE(`BOOTTIMRANGE)) bootdtim(.HSELTim(HSELBootTim), .HREADTim(HREADBootTim), .HRESPTim(HRESPBootTim), .HREADYTim(HREADYBootTim), .*); + dtim #(.BASE(`TIM_BASE), .RANGE(`TIM_RANGE)) dtim (.*); + dtim #(.BASE(`BOOTTIM_BASE), .RANGE(`BOOTTIM_RANGE)) bootdtim(.HSELTim(HSELBootTim), .HREADTim(HREADBootTim), .HRESPTim(HRESPBootTim), .HREADYTim(HREADYBootTim), .*); // memory-mapped I/O peripherals clint clint(.HADDR(HADDR[15:0]), .MTIME(MTIME_CLINT), .MTIMECMP(MTIMECMP_CLINT), .*); diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index e67606ec..f87f369b 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -582,8 +582,8 @@ string tests32f[] = '{ InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); // initialize tests - localparam integer MemStartAddr = `TIMBASE>>(1+`XLEN/32); - localparam integer MemEndAddr = (`TIMRANGE+`TIMBASE)>>1+(`XLEN/32); + localparam integer MemStartAddr = `TIM_BASE>>(1+`XLEN/32); + localparam integer MemEndAddr = (`TIM_RANGE+`TIM_BASE)>>1+(`XLEN/32); initial begin @@ -655,9 +655,9 @@ string tests32f[] = '{ errors = (i == SIGNATURESIZE+1); // error if file is empty i = 0; if (`XLEN == 32) - testadr = (`TIMBASE+tests[test+1].atohex())/4; + testadr = (`TIM_BASE+tests[test+1].atohex())/4; else - testadr = (`TIMBASE+tests[test+1].atohex())/8; + testadr = (`TIM_BASE+tests[test+1].atohex())/8; /* verilator lint_off INFINITELOOP */ while (signature[i] !== 'bx) begin //$display("signature[%h] = %h", i, signature[i]); diff --git a/wally-pipelined/testbench/testbench-privileged.sv b/wally-pipelined/testbench/testbench-privileged.sv index a10959b3..c3e8e20f 100644 --- a/wally-pipelined/testbench/testbench-privileged.sv +++ b/wally-pipelined/testbench/testbench-privileged.sv @@ -159,9 +159,9 @@ module testbench(); i = 0; errors = 0; if (`XLEN == 32) - testadr = (`TIMBASE+tests[test+1].atohex())/4; + testadr = (`TIM_BASE+tests[test+1].atohex())/4; else - testadr = (`TIMBASE+tests[test+1].atohex())/8; + testadr = (`TIM_BASE+tests[test+1].atohex())/8; /* verilator lint_off INFINITELOOP */ while (signature[i] !== 'bx) begin //$display("signature[%h] = %h", i, signature[i]); From df7e373c697c3976e711487ad7f2f49a51a9aa97 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 18 Jun 2021 08:13:15 -0400 Subject: [PATCH 4/8] Cleaned up PMAAccessFult logic but it still doesn't accomdate TIM and BootTim depending on AccessRWX --- wally-pipelined/src/mmu/pmachecker.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/wally-pipelined/src/mmu/pmachecker.sv b/wally-pipelined/src/mmu/pmachecker.sv index 0aaa8b97..703bb81b 100644 --- a/wally-pipelined/src/mmu/pmachecker.sv +++ b/wally-pipelined/src/mmu/pmachecker.sv @@ -70,9 +70,9 @@ module pmachecker ( assign AtomicAllowed = HSELRegions[4]; // Detect access faults - assign PMAAccessFault = ~|HSELRegions; + assign PMAAccessFault = (~|HSELRegions) && AccessRWX; assign PMAInstrAccessFaultF = ExecuteAccessF && PMAAccessFault; assign PMALoadAccessFaultM = ReadAccessM && PMAAccessFault; assign PMAStoreAccessFaultM = WriteAccessM && PMAAccessFault; - assign PMASquashBusAccess = PMAAccessFault && AccessRWX; + assign PMASquashBusAccess = PMAAccessFault; endmodule From faae30c31ca943acaea6bfad28d712fab177f5f1 Mon Sep 17 00:00:00 2001 From: bbracker Date: Fri, 18 Jun 2021 08:15:19 -0400 Subject: [PATCH 5/8] remove unused testbench-busybear.sv --- .../testbench/testbench-busybear.sv | 716 ------------------ 1 file changed, 716 deletions(-) delete mode 100644 wally-pipelined/testbench/testbench-busybear.sv diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv deleted file mode 100644 index c3c84de2..00000000 --- a/wally-pipelined/testbench/testbench-busybear.sv +++ /dev/null @@ -1,716 +0,0 @@ -`include "wally-config.vh" - - -module testbench(); - logic clk, reset; - logic [31:0] GPIOPinsIn; - logic [31:0] GPIOPinsOut, GPIOPinsEn; - - // instantiate device to be tested - logic [31:0] CheckInstrD; - - logic [`AHBW-1:0] HRDATA; - logic [31:0] HADDR; - logic [`AHBW-1:0] HWDATA; - logic HWRITE; - logic [2:0] HSIZE; - logic [2:0] HBURST; - logic [3:0] HPROT; - logic [1:0] HTRANS; - logic HMASTLOCK; - logic HCLK, HRESETn; - logic [`AHBW-1:0] HRDATAEXT; - logic HREADYEXT, HRESPEXT; - logic UARTSout; - - assign GPIOPinsIn = 0; - assign UARTSin = 1; - - // instantiate processor and memories - wallypipelinedsoc dut(.*); - - /** - * Walk the page table stored in dtim according to sv39 logic and translate a - * virtual address to a physical address. - * - * See section 4.3.2 of the RISC-V Privileged specification for a full - * explanation of the below algorithm. - */ - function logic [`XLEN-1:0] adrTranslator( - input logic [`XLEN-1:0] adrIn); - begin - logic SvMode, PTE_R, PTE_X; - logic [`XLEN-1:0] SATP, PTE; - logic [55:0] BaseAdr, PAdr; - logic [8:0] VPN [0:2]; - logic [11:0] Offset; - - int i; - - // Grab the SATP register from privileged unit - SATP = dut.hart.priv.csr.SATP_REGW; - - // Split the virtual address into page number segments and offset - VPN[2] = adrIn[38:30]; - VPN[1] = adrIn[29:21]; - VPN[0] = adrIn[20:12]; - Offset = adrIn[11:0]; - - // We do not support sv48; only sv39 - SvMode = SATP[63]; - - // Only perform translation if translation is on and the processor is not - // in machine mode - if (SvMode && (dut.hart.priv.PrivilegeModeW != `M_MODE)) begin - BaseAdr = SATP[43:0] << 12; - - for (i = 2; i >= 0; i--) begin - PAdr = BaseAdr + (VPN[i] << 3); - - // dtim.RAM is 64-bit addressed. PAdr specifies a byte. We right shift - // by 3 (the PTE size) to get the requested 64-bit PTE. - PTE = dut.uncore.dtim.RAM[PAdr >> 3]; - PTE_R = PTE[1]; - PTE_X = PTE[3]; - if (PTE_R || PTE_X) begin - // Leaf page found - break; - end else begin - // Go to next level of table - BaseAdr = PTE[53:10] << 12; - end - end - - // Determine which parts of the PTE page number to use based on the - // level of the page table we reached. - if (i == 2) begin - // Gigapage - assign adrTranslator = {8'b0, PTE[53:28], VPN[1], VPN[0], Offset}; - end else if (i == 1) begin - // Megapage - assign adrTranslator = {8'b0, PTE[53:19], VPN[0], Offset}; - end else begin - // Kilopage - assign adrTranslator = {8'b0, PTE[53:10], Offset}; - end - end else begin - // Direct translation if address translation is not on - assign adrTranslator = adrIn; - end - end - endfunction - - // initialize test - initial - begin - reset <= 1; # 22; reset <= 0; - end - - // read pc trace file - integer data_file_PC, scan_file_PC; - initial begin - data_file_PC = $fopen({`LINUX_TEST_VECTORS,"parsedPC.txt"}, "r"); - if (data_file_PC == 0) begin - $display("file couldn't be opened"); - $stop; - end - end - - integer data_file_PCW, scan_file_PCW; - initial begin - data_file_PCW = $fopen({`LINUX_TEST_VECTORS,"parsedPC.txt"}, "r"); - if (data_file_PCW == 0) begin - $display("file couldn't be opened"); - $stop; - end - end - - // read register trace file - integer data_file_rf, scan_file_rf; - initial begin - data_file_rf = $fopen({`LINUX_TEST_VECTORS,"parsedRegs.txt"}, "r"); - if (data_file_rf == 0) begin - $display("file couldn't be opened"); - $stop; - end - end - - // read CSR trace file - integer data_file_csr, scan_file_csr; - initial begin - data_file_csr = $fopen({`LINUX_TEST_VECTORS,"parsedCSRs2.txt"}, "r"); - if (data_file_csr == 0) begin - $display("file couldn't be opened"); - $stop; - end - end - - // read memreads trace file - integer data_file_memR, scan_file_memR; - initial begin - data_file_memR = $fopen({`LINUX_TEST_VECTORS,"parsedMemRead.txt"}, "r"); - if (data_file_memR == 0) begin - $display("file couldn't be opened"); - $stop; - end - end - - // read memwrite trace file - integer data_file_memW, scan_file_memW; - initial begin - data_file_memW = $fopen({`LINUX_TEST_VECTORS,"parsedMemWrite.txt"}, "r"); - if (data_file_memW == 0) begin - $display("file couldn't be opened"); - $stop; - end - end - - // initial loading of memories - initial begin - $readmemh({`LINUX_TEST_VECTORS,"bootmem.txt"}, dut.uncore.bootdtim.RAM, 'h1000 >> 3); // load at address 0x1000, start of boot TIM - $readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM); - $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory); - $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory); - end - - integer warningCount = 0; - integer instrs; - - //logic[63:0] adrTranslation[4:0]; - //string translationType[4:0] = {"rf", "writeAdr", "PCW", "PC", "readAdr"}; - //initial begin - // for(int i=0; i<5; i++) begin - // adrTranslation[i] = 64'b0; - // end - //end - - //function logic equal(logic[63:0] adr, logic[63:0] adrExpected, integer func); - // if (adr[11:0] !== adrExpected[11:0]) begin - // equal = 1'b0; - // end else begin - // equal = 1'b1; - // if ((adr+adrTranslation[func]) !== adrExpected) begin - // adrTranslation[func] = adrExpected - adr; - // $display("warning: probably new address translation %x for %s at instr %0d", adrTranslation[func], translationType[func], instrs); - // warningCount += 1; - // end - // end - //endfunction - - // pretty sure this isn't necessary anymore, but keeping this for now since its easier - function logic equal(logic[63:0] adr, logic[63:0] adrExpected, integer func); - equal = adr === adrExpected; - endfunction - - - `define ERROR \ - #10; \ - $display("processed %0d instructions with %0d warnings", instrs, warningCount); \ - $stop; - - logic [63:0] pcExpected; - logic [63:0] regExpected; - integer regNumExpected; - logic [`XLEN-1:0] PCW; - - flopenr #(`XLEN) PCWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.PCM, PCW); - - genvar i; - generate - for(i=1; i<32; i++) begin - always @(dut.hart.ieu.dp.regf.rf[i]) begin - if ($time == 0) begin - scan_file_rf = $fscanf(data_file_rf, "%x\n", regExpected); - if (dut.hart.ieu.dp.regf.rf[i] != regExpected) begin - $display("%0t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.hart.ieu.dp.regf.rf[i], regExpected); - `ERROR - end - end else begin - scan_file_rf = $fscanf(data_file_rf, "%d\n", regNumExpected); - scan_file_rf = $fscanf(data_file_rf, "%x\n", regExpected); - if (i != regNumExpected) begin - $display("%0t ps, instr %0d: wrong register changed: %0d, %0d expected to switch to %x from %x", $time, instrs, i, regNumExpected, regExpected, dut.hart.ieu.dp.regf.rf[regNumExpected]); - `ERROR - end - if (~equal(dut.hart.ieu.dp.regf.rf[i],regExpected, 0)) begin - $display("%0t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.hart.ieu.dp.regf.rf[i], regExpected); - `ERROR - end - //if (dut.hart.ieu.dp.regf.rf[i] !== regExpected) begin - // force dut.hart.ieu.dp.regf.rf[i] = regExpected; - // release dut.hart.ieu.dp.regf.rf[i]; - //end - end - end - end - endgenerate - - // RAM and bootram are addressed in 64-bit blocks - this logic handles R/W - // including subwords. Brief explanation on signals: - // - // readMask: bitmask of bits to read / write, left-shifted to align with - // nearest 64-bit boundary - examples - // HSIZE = 0 -> readMask = 11111111 - // HSIZE = 1 -> readMask = 1111111111111111 - // - // In the linux boot, the processor spends the first ~5 instructions in - // bootram, before jr jumps to main RAM - - logic [63:0] readMask; - assign readMask = ((1 << (8*(1 << HSIZE))) - 1) << 8 * HADDR[2:0]; - - logic [`XLEN-1:0] readAdrExpected, readAdrTranslated; - - always @(dut.HRDATA) begin - #2; - if (dut.hart.MemRWM[1] - && (dut.hart.ebu.CaptureDataM) - && dut.HRDATA !== {64{1'bx}}) begin - //$display("%0t", $time); - if($feof(data_file_memR)) begin - $display("no more memR data to read"); - `ERROR - end - scan_file_memR = $fscanf(data_file_memR, "%x\n", readAdrExpected); - scan_file_memR = $fscanf(data_file_memR, "%x\n", HRDATA); - assign readAdrTranslated = adrTranslator(readAdrExpected); - if (~equal(HADDR,readAdrTranslated,4)) begin - $display("%0t ps, instr %0d: HADDR does not equal readAdrExpected: %x, %x", $time, instrs, HADDR, readAdrTranslated); - `ERROR - end - if ((readMask & HRDATA) !== (readMask & dut.HRDATA)) begin - if (HADDR inside `LINUX_FIX_READ) begin - //$display("warning %0t ps, instr %0d, adr %0d: forcing HRDATA to expected: %x, %x", $time, instrs, HADDR, HRDATA, dut.HRDATA); - force dut.uncore.HRDATA = HRDATA; - #9; - release dut.uncore.HRDATA; - warningCount += 1; - end else begin - $display("%0t ps, instr %0d: ExpectedHRDATA does not equal dut.HRDATA: %x, %x from address %x, %x", $time, instrs, HRDATA, dut.HRDATA, HADDR, HSIZE); - `ERROR - end - end - //end else if(dut.hart.MemRWM[1]) begin - // $display("%x, %x, %x, %t", HADDR, dut.PCF, dut.HRDATA, $time); - - end - - end - - logic [`XLEN-1:0] writeDataExpected, writeAdrExpected, writeAdrTranslated; - - // this might need to change - //always @(HWDATA or HADDR or HSIZE or HWRITE) begin - always @(negedge HWRITE) begin - //#1; - if ($time != 0) begin - if($feof(data_file_memW)) begin - $display("no more memW data to read"); - `ERROR - end - scan_file_memW = $fscanf(data_file_memW, "%x\n", writeDataExpected); - scan_file_memW = $fscanf(data_file_memW, "%x\n", writeAdrExpected); - assign writeAdrTranslated = adrTranslator(writeAdrExpected); - - if (writeDataExpected != HWDATA && ~dut.uncore.HSELPLICD) begin - $display("%0t ps, instr %0d: HWDATA does not equal writeDataExpected: %x, %x", $time, instrs, HWDATA, writeDataExpected); - `ERROR - end - if (~equal(writeAdrTranslated,HADDR,1) && ~dut.uncore.HSELPLICD) begin - $display("%0t ps, instr %0d: HADDR does not equal writeAdrExpected: %x, %x", $time, instrs, HADDR, writeAdrTranslated); - `ERROR - end - end - end - - integer totalCSR = 0; - logic [99:0] StartCSRexpected[63:0]; - string StartCSRname[99:0]; - initial begin - while(1) begin - scan_file_csr = $fscanf(data_file_csr, "%s\n", StartCSRname[totalCSR]); - if(StartCSRname[totalCSR] == "---") begin - break; - end - scan_file_csr = $fscanf(data_file_csr, "%x\n", StartCSRexpected[totalCSR]); - totalCSR = totalCSR + 1; - end - end - - always @(dut.hart.priv.csr.genblk1.csrm.MCAUSE_REGW) begin - if (dut.hart.priv.csr.genblk1.csrm.MCAUSE_REGW == 2 && instrs > 1) begin - $display("!!!!!! illegal instruction !!!!!!!!!!"); - $display("(as a reminder, MCAUSE and MEPC are set by this)"); - $display("at %0t ps, instr %0d, HADDR %x", $time, instrs, HADDR); - `ERROR - end - if (dut.hart.priv.csr.genblk1.csrm.MCAUSE_REGW == 5 && instrs != 0) begin - $display("!!!!!! illegal (physical) memory access !!!!!!!!!!"); - $display("(as a reminder, MCAUSE and MEPC are set by this)"); - $display("at %0t ps, instr %0d, HADDR %x", $time, instrs, HADDR); - `ERROR - end - end - - `define CHECK_CSR2(CSR, PATH) \ - string CSR; \ - logic [63:0] expected``CSR``; \ - //CSR checking \ - always @(``PATH``.``CSR``_REGW) begin \ - if ($time > 1) begin \ - if ("SEPC" == `"CSR`") begin #1; end \ - if ("SCAUSE" == `"CSR`") begin #2; end \ - if ("SSTATUS" == `"CSR`") begin #3; end \ - scan_file_csr = $fscanf(data_file_csr, "%s\n", CSR); \ - scan_file_csr = $fscanf(data_file_csr, "%x\n", expected``CSR``); \ - if(CSR.icompare(`"CSR`")) begin \ - $display("%0t ps, instr %0d: %s changed, expected %s", $time, instrs, `"CSR`", CSR); \ - end \ - if(``PATH``.``CSR``_REGW != ``expected``CSR) begin \ - $display("%0t ps, instr %0d: %s does not equal %s expected: %x, %x", $time, instrs, `"CSR`", CSR, ``PATH``.``CSR``_REGW, ``expected``CSR); \ - `ERROR \ - end \ - end else begin \ - if (!(`BUILDROOT == 1 && "MSTATUS" == `"CSR`")) begin \ - for(integer j=0; j Date: Fri, 18 Jun 2021 09:11:31 -0400 Subject: [PATCH 6/8] Changed physical addresses to PA_BITS in size in MMU and TLB --- wally-pipelined/src/dmem/dmem.sv | 16 ++++++++++++---- wally-pipelined/src/ifu/ifu.sv | 11 ++++++++++- wally-pipelined/src/mmu/mmu.sv | 2 +- wally-pipelined/src/mmu/tlb.sv | 8 +++----- 4 files changed, 26 insertions(+), 11 deletions(-) diff --git a/wally-pipelined/src/dmem/dmem.sv b/wally-pipelined/src/dmem/dmem.sv index d05d592c..65791300 100644 --- a/wally-pipelined/src/dmem/dmem.sv +++ b/wally-pipelined/src/dmem/dmem.sv @@ -87,6 +87,8 @@ module dmem ( logic [1:0] CurrState, NextState; logic preCommittedM; + logic [`PA_BITS-1:0] MemPAdrMmmu; + localparam STATE_READY = 0; localparam STATE_FETCH = 1; localparam STATE_FETCH_AMO = 2; @@ -95,10 +97,16 @@ module dmem ( logic PMPInstrAccessFaultF, PMAInstrAccessFaultF; // *** these are just so that the mmu has somewhere to put these outputs since they aren't used in dmem // *** if you're allowed to parameterize outputs/ inputs existence, these are an easy delete. + generate + if (`XLEN==32) + assign MemPAdrM = MemPAdrMmmu[31:0]; + else + assign MemPAdrM = {8'b0, MemPAdrMmmu}; + endgenerate mmu #(.ENTRY_BITS(`DTLB_ENTRY_BITS), .IMMU(0)) dmmu(.TLBAccessType(MemRWM), .VirtualAddress(MemAdrM), .PTEWriteVal(PageTableEntryM), .PageTypeWriteVal(PageTypeM), .TLBWrite(DTLBWriteM), .TLBFlush(DTLBFlushM), - .PhysicalAddress(MemPAdrM), .TLBMiss(DTLBMissM), + .PhysicalAddress(MemPAdrMmmu), .TLBMiss(DTLBMissM), .TLBHit(DTLBHitM), .TLBPageFault(DTLBPageFaultM), .ExecuteAccessF(1'b0), @@ -142,20 +150,20 @@ module dmem ( // Handle atomic load reserved / store conditional generate if (`A_SUPPORTED) begin // atomic instructions supported - logic [`XLEN-1:2] ReservationPAdrW; + logic [`PA_BITS-1:2] ReservationPAdrW; logic ReservationValidM, ReservationValidW; logic lrM, scM, WriteAdrMatchM; assign lrM = MemReadM && AtomicM[0]; assign scM = MemRWM[0] && AtomicM[0]; - assign WriteAdrMatchM = MemRWM[0] && (MemPAdrM[`XLEN-1:2] == ReservationPAdrW) && ReservationValidW; + assign WriteAdrMatchM = MemRWM[0] && (MemPAdrM[`PA_BITS-1:2] == ReservationPAdrW) && ReservationValidW; assign SquashSCM = scM && ~WriteAdrMatchM; always_comb begin // ReservationValidM (next value of valid reservation) if (lrM) ReservationValidM = 1; // set valid on load reserve else if (scM || WriteAdrMatchM) ReservationValidM = 0; // clear valid on store to same address or any sc else ReservationValidM = ReservationValidW; // otherwise don't change valid end - flopenrc #(`XLEN-2) resadrreg(clk, reset, FlushW, lrM, MemPAdrM[`XLEN-1:2], ReservationPAdrW); // could drop clear on this one but not valid + flopenrc #(`PA_BITS-2) resadrreg(clk, reset, FlushW, lrM, MemPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid flopenrc #(1) resvldreg(clk, reset, FlushW, lrM, ReservationValidM, ReservationValidW); flopenrc #(1) squashreg(clk, reset, FlushW, ~StallW, SquashSCM, SquashSCW); end else begin // Atomic operations not supported diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index 29d77f09..ca0071b1 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -105,10 +105,19 @@ module ifu ( logic PMPLoadAccessFaultM, PMPStoreAccessFaultM; // *** these are just so that the mmu has somewhere to put these outputs, they're unused in this stage // if you're allowed to parameterize outputs/ inputs existence, these are an easy delete. + logic [`PA_BITS-1:0] PCPFmmu; + + generate + if (`XLEN==32) + assign PCPF = PCPFmmu[31:0]; + else + assign PCPF = {8'b0, PCPFmmu}; + endgenerate + mmu #(.ENTRY_BITS(`ITLB_ENTRY_BITS), .IMMU(1)) itlb(.TLBAccessType(2'b10), .VirtualAddress(PCF), .PTEWriteVal(PageTableEntryF), .PageTypeWriteVal(PageTypeF), .TLBWrite(ITLBWriteF), .TLBFlush(ITLBFlushF), - .PhysicalAddress(PCPF), .TLBMiss(ITLBMissF), + .PhysicalAddress(PCPFmmu), .TLBMiss(ITLBMissF), .TLBHit(ITLBHitF), .TLBPageFault(ITLBInstrPageFaultF), .AtomicAccessM(1'b0), .WriteAccessM(1'b0), .ReadAccessM(1'b0), // *** is this the right way force these bits constant? should they be someething else? diff --git a/wally-pipelined/src/mmu/mmu.sv b/wally-pipelined/src/mmu/mmu.sv index 3efc4cef..04deb694 100644 --- a/wally-pipelined/src/mmu/mmu.sv +++ b/wally-pipelined/src/mmu/mmu.sv @@ -57,7 +57,7 @@ module mmu #(parameter ENTRY_BITS = 3, input logic TLBFlush, // Physical address outputs - output logic [`XLEN-1:0] PhysicalAddress, + output logic [`PA_BITS-1:0] PhysicalAddress, output logic TLBMiss, output logic TLBHit, diff --git a/wally-pipelined/src/mmu/tlb.sv b/wally-pipelined/src/mmu/tlb.sv index 86fe6f86..127dc5a5 100644 --- a/wally-pipelined/src/mmu/tlb.sv +++ b/wally-pipelined/src/mmu/tlb.sv @@ -78,7 +78,7 @@ module tlb #(parameter ENTRY_BITS = 3, input logic TLBFlush, // Physical address outputs - output logic [`XLEN-1:0] PhysicalAddress, + output logic [`PA_BITS-1:0] PhysicalAddress, output logic TLBMiss, output logic TLBHit, @@ -202,11 +202,9 @@ module tlb #(parameter ENTRY_BITS = 3, // Output the hit physical address if translation is currently on. generate if (`XLEN == 32) begin - // *** If we want rv32 to use the full 34 bit physical address space, this - // must be changed - mux2 #(`XLEN) addressmux(VirtualAddress, PhysicalAddressFull[31:0], Translate, PhysicalAddress); + mux2 #(`PA_BITS) addressmux({2'b0, VirtualAddress}, PhysicalAddressFull, Translate, PhysicalAddress); end else begin - mux2 #(`XLEN) addressmux(VirtualAddress, {8'b0, PhysicalAddressFull}, Translate, PhysicalAddress); + mux2 #(`PA_BITS) addressmux(VirtualAddress[`PA_BITS-1:0], PhysicalAddressFull, Translate, PhysicalAddress); end endgenerate From 580ac1c4df12dbca650c54ad4f43eac8f873b663 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 18 Jun 2021 09:36:22 -0400 Subject: [PATCH 7/8] Made MemPAdrM and related signals PA_BITS wide --- wally-pipelined/src/dmem/dcache.sv | 12 ++++++------ wally-pipelined/src/dmem/dmem.sv | 12 ++---------- wally-pipelined/src/ebu/ahblite.sv | 2 +- wally-pipelined/src/wally/wallypipelinedhart.sv | 3 ++- 4 files changed, 11 insertions(+), 18 deletions(-) diff --git a/wally-pipelined/src/dmem/dcache.sv b/wally-pipelined/src/dmem/dcache.sv index 243c6975..fec70ef4 100644 --- a/wally-pipelined/src/dmem/dcache.sv +++ b/wally-pipelined/src/dmem/dcache.sv @@ -31,7 +31,7 @@ module dcache( input logic StallW, input logic FlushW, // Upper bits of physical address - input logic [`XLEN-1:12] UpperPAdrM, + input logic [`PA_BITS-1:12] UpperPAdrM, // Lower 12 bits of virtual address, since it's faster this way input logic [11:0] LowerVAdrM, // Write to the dcache @@ -41,7 +41,7 @@ module dcache( input logic [`XLEN-1:0] ReadDataW, input logic MemAckW, // Access requested from the ebu unit - output logic [`XLEN-1:0] MemPAdrM, + output logic [`PA_BITS-1:0] MemPAdrM, output logic MemReadM, MemWriteM, // High if the dcache is requesting a stall output logic DCacheStallW, @@ -56,7 +56,7 @@ module dcache( // Input signals to cache memory logic FlushMem; - logic [`XLEN-1:12] DCacheMemUpperPAdr; + logic [`PA_BITS-1:12] DCacheMemUpperPAdr; logic [11:0] DCacheMemLowerAdr; logic DCacheMemWriteEnable; logic [DCACHELINESIZE-1:0] DCacheMemWriteData; @@ -98,7 +98,7 @@ module dcachecontroller #(parameter LINESIZE = 256) ( // Input the address to read // The upper bits of the physical pc - input logic [`XLEN-1:12] DCacheMemUpperPAdr, + input logic [`PA_BITS-1:12] DCacheMemUpperPAdr, // The lower bits of the virtual pc input logic [11:0] DCacheMemLowerAdr, @@ -122,7 +122,7 @@ module dcachecontroller #(parameter LINESIZE = 256) ( input logic [`XLEN-1:0] ReadDataW, input logic MemAckW, // The read we request from main memory - output logic [`XLEN-1:0] MemPAdrM, + output logic [`PA_BITS-1:0] MemPAdrM, output logic MemReadM, MemWriteM ); @@ -144,7 +144,7 @@ module dcachecontroller #(parameter LINESIZE = 256) ( logic FetchState, BeginFetchState; logic [LOGWPL:0] FetchWordNum, NextFetchWordNum; - logic [`XLEN-1:0] LineAlignedPCPF; + logic [`PA_BITS-1:0] LineAlignedPCPF; flopr #(1) FetchStateFlop(clk, reset, BeginFetchState | (FetchState & ~EndFetchState), FetchState); flopr #(LOGWPL+1) FetchWordNumFlop(clk, reset, NextFetchWordNum, FetchWordNum); diff --git a/wally-pipelined/src/dmem/dmem.sv b/wally-pipelined/src/dmem/dmem.sv index 65791300..ba3617d0 100644 --- a/wally-pipelined/src/dmem/dmem.sv +++ b/wally-pipelined/src/dmem/dmem.sv @@ -40,7 +40,7 @@ module dmem ( input logic [`XLEN-1:0] WriteDataM, input logic [1:0] AtomicM, input logic CommitM, - output logic [`XLEN-1:0] MemPAdrM, + output logic [`PA_BITS-1:0] MemPAdrM, output logic MemReadM, MemWriteM, output logic [1:0] AtomicMaskedM, output logic DataMisalignedM, @@ -87,8 +87,6 @@ module dmem ( logic [1:0] CurrState, NextState; logic preCommittedM; - logic [`PA_BITS-1:0] MemPAdrMmmu; - localparam STATE_READY = 0; localparam STATE_FETCH = 1; localparam STATE_FETCH_AMO = 2; @@ -97,16 +95,10 @@ module dmem ( logic PMPInstrAccessFaultF, PMAInstrAccessFaultF; // *** these are just so that the mmu has somewhere to put these outputs since they aren't used in dmem // *** if you're allowed to parameterize outputs/ inputs existence, these are an easy delete. - generate - if (`XLEN==32) - assign MemPAdrM = MemPAdrMmmu[31:0]; - else - assign MemPAdrM = {8'b0, MemPAdrMmmu}; - endgenerate mmu #(.ENTRY_BITS(`DTLB_ENTRY_BITS), .IMMU(0)) dmmu(.TLBAccessType(MemRWM), .VirtualAddress(MemAdrM), .PTEWriteVal(PageTableEntryM), .PageTypeWriteVal(PageTypeM), .TLBWrite(DTLBWriteM), .TLBFlush(DTLBFlushM), - .PhysicalAddress(MemPAdrMmmu), .TLBMiss(DTLBMissM), + .PhysicalAddress(MemPAdrM), .TLBMiss(DTLBMissM), .TLBHit(DTLBHitM), .TLBPageFault(DTLBPageFaultM), .ExecuteAccessF(1'b0), diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv index ea76556c..88e8f27a 100644 --- a/wally-pipelined/src/ebu/ahblite.sv +++ b/wally-pipelined/src/ebu/ahblite.sv @@ -47,7 +47,7 @@ module ahblite ( output logic [`XLEN-1:0] InstrRData, output logic InstrAckF, // Signals from Data Cache - input logic [`XLEN-1:0] MemPAdrM, + input logic [`PA_BITS-1:0] MemPAdrM, input logic MemReadM, MemWriteM, input logic [`XLEN-1:0] WriteDataM, input logic [1:0] MemSizeM, diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 2535eef3..c2dfd437 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -135,7 +135,8 @@ module wallypipelinedhart ( logic MemReadM, MemWriteM; logic [1:0] AtomicMaskedM; logic [2:0] Funct3M; - logic [`XLEN-1:0] MemAdrM, MemPAdrM, WriteDataM; + logic [`XLEN-1:0] MemAdrM, WriteDataM; + logic [`PA_BITS-1:0] MemPAdrM; logic [`XLEN-1:0] ReadDataW; logic [`XLEN-1:0] InstrPAdrF; logic [`XLEN-1:0] InstrRData; From 4f50dd575d67bce261a828d015725a7e6236a88d Mon Sep 17 00:00:00 2001 From: bbracker Date: Fri, 18 Jun 2021 09:49:30 -0400 Subject: [PATCH 8/8] buildroot added to regression because it passes regression --- wally-pipelined/regression/regression-wally.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/wally-pipelined/regression/regression-wally.py b/wally-pipelined/regression/regression-wally.py index 5b45f9a5..d3afe6ed 100755 --- a/wally-pipelined/regression/regression-wally.py +++ b/wally-pipelined/regression/regression-wally.py @@ -28,11 +28,11 @@ configs = [ cmd="vsim -do wally-busybear-batch.do -c > {}", grepstr="# loaded 100000 instructions" ), -# TestCase( -# name="buildroot", -# cmd="vsim -do wally-buildroot-batch.do -c > {}", -# grepstr="# loaded 100000 instructions" -# ), + TestCase( + name="buildroot", + cmd="vsim -do wally-buildroot-batch.do -c > {}", + grepstr="# loaded 600000 instructions" + ), TestCase( name="rv32ic", cmd="vsim > {} -c <