From e34b8139af456f0f197e635d7944c84cdd92cf27 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 27 Dec 2022 06:35:17 -0800
Subject: [PATCH] Check for non-negative W in int sign handling

---
 pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 10 +++++-----
 pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv  |  1 +
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
index 7cdf66d1..07d71ba8 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
@@ -56,7 +56,7 @@ module fdivsqrtpostproc(
   logic [`DIVb:0] NormQuotM;
   logic [`DIVb+3:0] IntQuotM, IntRemM, NormRemM;
   logic signed [`DIVb+3:0] PreResultM, PreFPIntDivResultM;
-  logic [`XLEN-1:0] W64FPIntDivResultM;
+  logic [`XLEN-1:0] SpecialFPIntDivResultM;
 
   //////////////////////////
   // Execute Stage: Detect early termination for an exact result
@@ -113,8 +113,7 @@ module fdivsqrtpostproc(
         NormRemM  = W;
       end
     else 
-//      if (NegStickyM | weq0) begin // *** old code, replaced by the one below in the right stage and more comprehensive
-      if (NegStickyM | WZeroM) begin
+      if (NegStickyM) begin
         NormQuotM = FirstUM;
         NormRemM  = -(W + DM);
       end else begin 
@@ -166,8 +165,9 @@ module fdivsqrtpostproc(
    // division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted
   
   assign PreFPIntDivResultM = $signed(PreResultM >>> NormShiftM);
-  assign W64FPIntDivResultM = (W64M ? {{(`XLEN-32){PreFPIntDivResultM[31]}}, PreFPIntDivResultM[31:0]} : PreFPIntDivResultM[`XLEN-1:0]); // Sign extending in case of W64
-  assign FPIntDivResultM = BZeroM ? (RemOpM ? ForwardedSrcAM : {(`XLEN){1'b1}}) : W64FPIntDivResultM; // special cases
+  assign SpecialFPIntDivResultM = BZeroM ? (RemOpM ? ForwardedSrcAM : {(`XLEN){1'b1}}) : PreFPIntDivResultM[`XLEN-1:0]; // special cases
+  // *** conditional on RV64
+  assign FPIntDivResultM = (W64M ? {{(`XLEN-32){SpecialFPIntDivResultM[31]}}, SpecialFPIntDivResultM[31:0]} : SpecialFPIntDivResultM[`XLEN-1:0]); // Sign extending in case of W64
  
   assign PreQmM = NegStickyM ? FirstUM : FirstU; // Select U or U-1 depending on negative sticky bit
   assign QmM = SqrtM ? (PreQmM << 1) : PreQmM;
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
index e011bf7d..1f4ac4ea 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
@@ -69,6 +69,7 @@ module fdivsqrtpreproc (
   // ***can probably merge X LZC with conversion
   // cout the number of leading zeros
 
+  // *** W64 muxes conditional on RV64
   assign AsE = ~Funct3E[0] & (W64E ? ForwardedSrcAE[31] : ForwardedSrcAE[`XLEN-1]);
   assign BsE = ~Funct3E[0] & (W64E ? ForwardedSrcBE[31] : ForwardedSrcBE[`XLEN-1]);
   assign A64 = W64E ? {{(`XLEN-32){AsE}}, ForwardedSrcAE[31:0]} : ForwardedSrcAE;